LAN9217-MT-E2 SMSC [SMSC Corporation], LAN9217-MT-E2 Datasheet - Page 92

• Manufacturer Part Number: LAN9217-MT-E2
• Description: 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Revision 1.5 (07-18-06)
5.3.20
5.3.21
BITS
BITS
29-8
31-0
7-0
31
30
CSR Busy. When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
R/nW. When set, this bit indicates that the host is requesting a read
operation. When clear, the host is performing a write.
Reserved.
CSR Address. The 8-bit value in this field selects which MAC CSR will be
accessed with the read or write operation.
MAC CSR Data. Value read from or written to the MAC CSR’s.
MAC_CSR_CMD – MAC CSR Synchronizer Command Register
This register is used to control the read and write operations with the MAC CSR’s
MAC_CSR_DATA – MAC CSR Synchronizer Data Register
This register is used in conjunction with the MAC_CSR_CMD register to perform read and write
operations with the MAC CSR’s
Offset:
Offset:
DESCRIPTION
DESCRIPTION
A4h
A8h
DATASHEET
92
16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Size:
Size:
32 bits
32 bits
TYPE
TYPE
R/W
R/W
R/W
SC
RO
SMSC LAN9217
00000000h
DEFAULT
DEFAULT
00h
Datasheet
0
0
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