SSD1339U3 ETC1 [List of Unclassifed Manufacturers], SSD1339U3 Datasheet - Page 20

• Manufacturer Part Number: SSD1339U3
• Description: 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

This module determines whether the input data is interpreted as data or command. Data is interpreted
based upon the input of the D/C# pin.
If D/C# pin is high, data is written to Graphic Display Data RAM (GDDRAM). If it is low, the input at D
is interpreted as a Command and it will be decoded and be written to the corresponding command
register.
The parallel interface consists of 18 bi-directional data pins (D
R/W#(WR#), D/C#, E (RD#) and CS#. R/W#(WR#) input High indicates a read operation from the Graphic
Display Data RAM (GDDRAM) or the status register. RW#/(WR#) input Low indicates a write operation to
Display Data RAM or Internal Command Registers depending on the status of D/C# input. The E(RD#)
input serves as data latch signal (clock) when high provided that CS# is low and high respectively. Refer
to .
Figure 32 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series
microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual
display data read. This is shown in Figure 6 below.
The parallel interface consists of 18 bi-directional data pins (D
(RD#), R/W#(WR#), D/C# and CS#. The E(RD#) input serves as data read latch signal (clock) when low,
provided that CS# is low and high respectively. Display data or status register read is controlled by D/C#.
R/W#(WR#) input serves as data write latch signal (clock) when high provided that CS# is low and high
respectively. Display data or command register write is controlled by D/C#. Refer to * when 8 bit used: D
~ D
~ D
Figure 33 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series
microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual
display data read.
Command Decoder and Command Interface
MPU Parallel 6800-series Interface
MPU Parallel 8080-series Interface
Solomon Systech
7
17
R/ W#(WR#)
instead; when 9 bit used: D
instead.
Data bus
E(RD#)
Figure 6 – Display data read back procedure - insertion of dummy read
Write column address
N
0
~ D
8
instead; when 16 bit used: D
Dummy read
Data read1
n
17
Jul 2005
17
-D
-D
0
0
) or 8 bi-directional data pins (D
) or 8 bi-directional data pins (D
0
~ D
15
n+1
Data read2
P 20/59 Rev 1.1
instead; when 18 bit used: D
Data read3
n+2
SSD1339
7
7
-D
-D
0
0
7
),
), E
0
-D
0
0