SSD1339U3 ETC1 [List of Unclassifed Manufacturers], SSD1339U3 Datasheet - Page 39

• Manufacturer Part Number: SSD1339U3
• Description: 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Pulse
Width
Front Clock Divider (DivSet)/ Oscillator Frequency (B3h)
This command consists of two functions:
Look Up Table for Gray Scale Pulse width (B8h)
This command is used to set the gray scale table for the display. Except gray scale entry 0, which is zero
as it has no pre-charge and current drive, each odd entry gray scale level is programmed in the length of
current drive stage pulse width with unit of DCLK. The longer the length of the pulse width, the brighter is
the OLED pixel when it’s turned on. Please refer to section “Graphic Display Data RAM (GDDRAM)” for
more detailed explanation of relation of display data RAM, gray scale table and the pixel brightness.
Following the command B8h, the user has to set the pulse width from PW1, PW3, PW5, …, PW59,
PW61, PW63 one by one in sequence and complies the following conditions.
Afterwards, the driver automatically derives the pulse width of even entry of gray scale table PW2, PW4,
…, PW62 with the formula like below.
For example, if PW1 = 3 DCLKs and PW3 = 7 DCLKs, PW2 = (3+7)/2 = 5 DCLKs
The setting of gray scale table entry can perform gamma correction on OLED panel display. Normally, it
is desired that the brightness response of the panel is linearly proportional to the image data value in
display data RAM. However, the OLED panel is somehow responded in non-linear way. Appropriate
gray scale table setting like example below can compensate this effect.
Use Built-in Linear LUT (B9h)
This command reloads the preset linear gray scale table as PW1 = 1, PW2 = 3, PW3 = 5, …., PW62 =
123, PW63 = 125 DCLKs.
SSD1339
Gray scale
table setting
Display Clock Divide Ratio (A[3:0])
Set the divide ratio to generate DCLK (Display Clock) from CLK. The divide ratio is from 1 to 16,
with power on reset value = 1. Please refer to section “Oscillator Circuit and Display Time
Generator” for the details of DCLK and CLK.
Oscillator Frequency (A[7:4])
Program the oscillator frequency Fosc which is the source of CLK if CLS pin is pulled high. The
4-bit value results in 16 different frequency setting available as shown below. The default value is
1101b.
Figure 25 – Example of gamma correction by gray scale table setting
Gray Scale
Rev 1.1
P 39/59 Jul 2005
PW1 > 0; PW3 > PW1 + 1; PW5 > PW3 + 1; ……
Brightness
PWn = (PWn-1 + PWn+1) / 2
Panel
response
Pulse width
Brightness
Result in linear
response
Gray Scale
Solomon Systech