SSD1339U3 ETC1 [List of Unclassifed Manufacturers], SSD1339U3 Datasheet - Page 24
SSD1339U3
Manufacturer Part Number
SSD1339U3
Description
132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller
Manufacturer
ETC1 [List of Unclassifed Manufacturers]
Datasheet
1.SSD1339U3.pdf
(59 pages)
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The sequence of sending 65K color depth pixel in 8-bit MCU interface is divided into two 8-bit sessions as
shown below.
With reference to Figure 8 conventions, in writing the data into graphic display data RAM, the bit positions
filled by the input data for each color is shown below.
In data RAM, each data occupies 6-bit. However, color A and C have 5-bit length only in 65k color mode.
Therefore, RAM positions A0 and C0 are empty originally. These emptied positions are filled as shown
above to increase color A and C to 6-bit length in display data RAM.
Data access in 256 colors mode
In 256-color mode, each pixel is composed of 8-bit. Only 8-bit MCU interface is available to access
display data RAM. The communication session is done in 1 time by writing 8-bit data into RAM.
Figure 11 – 256 Color Depth Graphic Display Data Writing Sequence in 8-bit MCU Interface
With reference to Figure 8 conventions, in writing the data into graphic display data RAM, the bit positions
filled by the input data for each color is shown below.
Solomon Systech
Figure 16 – Display data RAM writing position for color A, B and C data input in 65k color mode
Figure 15 – 65k color depth graphic display data writing sequence in 8-bit MCU interface
Bit
1
2
Bit Position
Input Data
Bit Position
Input Data
Bit Position
Input Data
Bit
1
Bit Position
Input Data
Color A
Color B
Color C
Color A
st
nd
st
byte
byte
byte
C1
B1
A1
B1
C1
C1
A1
C5
A5
B5
A5
7
7
2
4
5
1
4
4
2
C1
B1
A1
B1
C1
C1
A1
A4
B4
C4
A4
6
6
1
3
4
0
3
3
1
C1
C1
C1
B1
A1
B1
A1
C3
A3
B3
A3
5
5
0
2
3
1
2
2
0
C1
A1
A1
B1
C1
B1
A1
A2
B2
C2
A2
4
4
4
1
2
2
1
1
1
Jul 2005
C1
C1
A1
A1
B1
B1
A1
C1
A1
B1
A1
3
3
3
0
1
1
1
0
0
B1
A1
A1
B1
C1
B1
A1
A0
B0
C0
A0
P 24/59 Rev 1.1
2
2
5
2
4
0
0
1
4
B1
A1
A1
1
1
4
1
1
B1
A1
A1
0
0
3
0
0
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