SSD1339U3 ETC1 [List of Unclassifed Manufacturers], SSD1339U3 Datasheet - Page 22

• Manufacturer Part Number: SSD1339U3
• Description: 132RGB x 132 with 2 smart Icon lines Dot Matrix OLED/PLED Segment/Common Driver with Controller
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Bit
Data bits
The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is
132 x 133 x 18bits.
For mechanical flexibility, re-mapping on both Segment and Common outputs can be selected by
software.
For vertical scrolling of the display, an internal register storing display start line can be set to control the
portion of the RAM data to be mapped to the display.
Each pixel has 18-bit data. Each sub-pixels for color A, B and C have 6 bits. The arrangement of data
pixel in graphic display data RAM is shown below.
Data access in 262k colors mode
In 262k colors depth mode, there are different MCU interface communication modes to access graphic
display data RAM in OLED driver.
For 18 bits mode, the communication is made up of one session of 18 data bits. MCU transmits all bits to
write one 18-bit pixel data into OLED driver. This 18-bit mode can be selected by setting the A[3] bit in
command A0 to 1.
For the 1
MCU transmits two 16-bit words to write one 18-bit pixel data into OLED driver. Mode 1 is selected by
setting A0h register A[7:6] bits to 10b. In below, A1, B1, C1 are pixel bits for color A, B and C, and “X”
stands for don’t care value.
Graphic Display Data RAM (GDDRAM)
Solomon Systech
Address
Column
Normal
SEG OUTPUT
130
131
132
0
1
2
17
C
:
Address
Format
5
Data
Row
Normal
Remap
Remap
st
16
C
132
131
130
2
1
0
:
4
option of the two 16-bit modes, the communication is divided into two sessions of 16 data bits.
Figure 9 – 262k color depth data writing sequence in 18-bit MCU interface
SA0 SB0 SC0 SA1 SB1 SC1 SA2 SB2 SC2
A5
A4
A3
A2
A1
A0
15
C
6
3
131
B5
B4
B3
B2
B1
B0
0
6
14
C
no. of bits of data in this cell
C5
C4
C3
C2
C1
C0
2
6
Figure 8 – Graphic Display Data RAM Structure
A5
A4
A3
A2
A1
A0
13
C
6
1
130
B5
B4
B3
B2
B1
B0
1
6
12
C
C4
C3
C2
C1
C0
0
C5
6
11
A4
A3
A2
A1
A0
B
A5
6
5
129
B5
B4
B3
B2
B1
B0
2
6
10
B
4
C5
C4
C3
C2
C1
C0
6
B
9
:
:
:
:
:
:
3
SA129 SB129 SC129 SA130 SB130 SC130 SA131 SB131 SC131
A4
A3
A2
A1
A0
A5
6
B
8
Jul 2005
2
B5
B4
B3
B2
B1
B0
129
2
6
C5
C4
C3
C2
C1
C0
B
7
6
1
A4
A3
A2
A1
A0
A5
6
P 22/59 Rev 1.1
B
6
0
130
B5
B4
B3
B2
B1
B0
1
6
A
C5
C4
C3
C2
C1
C0
5
6
5
A4
A3
A2
A1
A0
A5
6
A
4
4
131
B5
B4
B3
B2
B1
B0
0
6
A
C5
C4
C3
C2
C1
C0
3
6
3
SSD1339
COM131
COM130
COM132
OUTPUT
COM0
COM1
COM2
A
2
COM
2
:
A
1
1
A
0
0