LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet
LH540235M-20
Related parts for LH540235M-20
LH540235M-20 Summary of contents
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LH540235/45 FEATURES Fast Cycle Times: 20/25/35 ns Pin-Compatible Drop-In Replacements for IDT72235B/45B FIFOs Choice of IDT-Compatible or Enhanced Operating Mode; Selected by an Input Control Signal Device Comes Up into One of Two Known Default States at Reset Depending on ...
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LH540235/45 FUNCTIONAL DESCRIPTION NOTE: Throughout this data sheet, a BOLD ITALIC type font is used for all references to Enhanced Operating Mode features which do not function in IDT-Compatible Operating Mode; and also for all references to the re- transmit ...
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Synchronous FIFOs In the Enhanced Operating Mode, coordinated op- eration of two 18-bit FIFOs as one 36-bit FIFO may be ensured by ‘interlocked’ crosscoupling of the status- flag outputs from each FIFO to the expansion ...
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LH540235/45 64-PIN TQFP ...
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Synchronous FIFOs PIN LIST SIGNAL NAME PLCC PIN NO REN 4 RCLK ...
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LH540235/45 PIN DESCRIPTIONS PIN PIN NAME TYPE D – D Data Inputs Reset Enhanced EMODE Operating Mode WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable OE Output Enable BOLD ITALIC = Enhanced Operating ...
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Synchronous FIFOs PIN DESCRIPTIONS (cont’d) PIN PIN NAME TYPE LD Load I WEN Write Enable REN Read Enable Full Flag O Programmable PAF O Almost-Full Flag HF Half-Full ...
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LH540235/45 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage to V Potential –0 Signal Pin Voltage to V Potential –0 Output Current Temperature Range with Power – 125 C ...
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Synchronous FIFOs AC ELECTRICAL CHARACTERISTICS SYMBOL f Clock Cycle Frequency CC t Data Access Time A t Clock Cycle Time CLK t Clock HIGH Time CLKH t Clock LOW Time CLKL t Data Setup Time ...
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LH540235/45 DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES EMODE WXI/ WEN RXI/ REN FL ...
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Synchronous FIFOs Table 3. Selection of Read and Write Operations 3,4 3,4 LD WEN REN WCLK – ...
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LH540235/45 NUMBER OF UNREAD DATA WORDS PRESENT WITHIN FIFO 2048 18 FIFO 1024 1025 to (2048 – 1)) 2049 to (4096 – 1)) (2048 – 2047 ...
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Synchronous FIFOs DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d) COMMAND VALUE AFTER RESET REGISTER CODE EMODE = H EMODE = L BITS 03 ...
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LH540235/45 Data Inputs DATA IN (D – Data, programmable-flag-offset values, and Control- Register codes are input to the FIFO as 18-bit words on D – Unused bit positions in offset-value and Con ...
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Synchronous FIFOs DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d) READ CLOCK (RCLK) A rising edge (LOW-to-HIGH transition) of RCLK initi- ates a FIFO read cycle HIGH programma- ble-register read cycle ...
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LH540235/45 WORD 0 17 WORD 1 17 WORD 2 17 CONTROL-REGISTER BITS: 6 Future use to control depth cascading and interlocked paralleling. 5 Enables suppressing reading whenever data outputs are disabled. 4 Makes PAF synchronous Makes HF synchronous. ...
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Synchronous FIFOs DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d) What happens next is determined by the state of the EMODE control input deasserted (HIGH), the next 18-bit word from the data inputs ...
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LH540235/45 WRITE EXPANSION INPUT/ WRITE ENABLE 2 (WXI/ WEN ) 2 WXI /WEN is a dual-purpose signal one of four 2 input signals which select the grouping mode in which the FIFO operates after being reset; the other ...
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Synchronous FIFOs DESCRIPTION OF SIGNALS AND OPERATING SEQUENCES (cont’d) The default value of ‘p’ after the completion of a reset operation is 127 . However, ‘p’ may be set to any value 10 which does ...
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LH540235/45 PROGRAMMABLE ALMOST-EMPTY FLAG (PAE) PAE goes LOW whenever the FIFO is ‘almost empty’; that is, whenever subtracting the value of the FIFO’s internal write pointer from the value of its internal read pointer yields a difference which is less ...
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Synchronous FIFOs TIMING DIAGRAMS RS REN, WEN, LD EF, PAE FF, PAF NOTES: 1. After reset, the outputs will be LOW LOW, and in a high-impedance ...
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LH540235/45 TIMING DIAGRAMS (cont’d) RCLK REN SKEW2 WCLK WEN NOTE the minimum time between a rising WCLK edge and a SKEW2 rising RCLK edge for EF to change predictably ...
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Synchronous FIFOs TIMING DIAGRAMS (cont’d) WCLK ENS WEN RCLK EF REN NOTES the minimum time between a rising ...
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LH540235/45 TIMING DIAGRAMS (cont’d) NO WRITE WCLK WEN RCLK t ENS t ENH REN LOW OE DATA OUTPUT REGISTER NOTE the minimum time between ...
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Synchronous FIFOs TIMING DIAGRAMS (cont’d) WCLK DATA WRITE ENS t ENH WEN t SKEW2 RCLK REN OE LOW DATA IN ...
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LH540235/45 TIMING DIAGRAMS (cont’d) t CLKH WCLK LD WEN Figure 12. Programmable-Register Write Operation t CLKH RCLK LD REN Figure 13. Programmable-Register Read Operation 26 t CLK t CLKL t ...
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Synchronous FIFOs TIMING DIAGRAMS (cont’d) WCLK WEN PAE RCLK REN NOTE: 1. PAE offset = q. Also, number of data words written into FIFO already = q. Figure 14. Programmable-Almost-Empty Flag Timing CLKH ...
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LH540235/45 TIMING DIAGRAMS (cont’d) Enhanced Operating Mode Timing Diagram A WCLK DATA WRITE ENS t ENH WEN t (1) SKEW2 RCLK PAE REN OE LOW DATA IN OUTPUT ...
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Synchronous FIFOs TIMING DIAGRAMS (cont’d) WCLK WEN PAF RCLK REN NOTES: 1. PAF offset = p. Number of data words written into FIFO already = 2047 - p for the LH540235 and 4095 - p ...
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LH540235/45 TIMING DIAGRAMS (cont’d) Enhanced Operating Mode Timing Diagram NO WRITE WCLK t (1) SKEW1 PAF WEN A RCLK t ENS t ENH REN LOW DATA ...
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Synchronous FIFOs TIMING DIAGRAMS (cont’d) WCLK WEN HF RCLK REN t t CLKH CLKL t ENS t ENH t HF HALF FULL +1 HALF FULL OR LESS OR MORE t ENS Figure 18. Half-Full-Flag Timing, ...
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LH540235/45 TIMING DIAGRAMS (cont’d) Enhanced Operating Mode Timing Diagram NO WRITE WCLK t SKEW1 WEN A RCLK t ENS t ENH REN LOW OE DATA OUTPUT REGISTER NOTES: ...
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Synchronous FIFOs TIMING DIAGRAMS (cont’d) Enhanced Operating Mode Timing Diagram A WCLK DATA WRITE ENS t ENH WEN (1) t SKEW2 RCLK HF REN OE LOW ...
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LH540235/45 TIMING DIAGRAMS (cont’d) Q [17: RCLK REN FL/RT t ENS PREVIOUS VALID FF FF PREVIOUS VALID PAF PAF PREVIOUS VALID HF HF PREVIOUS VALID PAE PAE PREVIOUS VALID EF EF ...
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Synchronous FIFOs TIMING DIAGRAMS (cont’d) WCLK WXO WEN NOTE: Write to last physical location. RCLK RXO REN NOTE: Read from last physical location. WXI WCLK t CLKH t XO (NOTE ENS Figure ...
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LH540235/45 TIMING DIAGRAMS (cont’d) RXI RCLK APPLICATIONS INFORMATION Standalone Configuration When depth cascading is not required for a given application, the LH540235/45 is placed in standalone mode by tying the two Expansion In pins WXI/ WEN RXI/ REN to ground, ...
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Synchronous FIFOs When standalone-mode LH540235/45 devices are paralleled, the behavior of the status flags is identical for all devices; so, in principle, a representative value for each of these flags could be derived from any ...
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LH540235/45 Figure 27. Interlocked-Paralleled Word-Width Expansion 38 2048 x 18/4096 x 18 Synchronous FIFOs ...
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Synchronous FIFOs 18 DATA WRITE CLOCK WRITE ENABLE RESET LOAD 18 FF (COMPOSITE FLAGS) PAF NOTES: Grounding FL designates the 'first-load' FIFO ('master' FIFO). The remaining FIFOs are 'slave' FIFOs. BOLD ITALIC ...
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LH540235/45 Depth Cascading Using Pipelining Using the pipelining approach, depth cascading is implemented by connecting the required number of LH540235/45s in series. Within the cascade, the Data Outputs of each device are connected to the Data Inputs of the next ...
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Synchronous FIFOs Figure 29. TI-Style Pipelined Depth-Cascading LH540235/45 41 ...
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LH540235/45 Figure 30. Interlocked Paralleling Used Together 42 2048 x 18/4096 x 18 Synchronous FIFOs With Pipelined Depth-Cascading ...
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Synchronous FIFOs PACKAGE DIAGRAMS 68PLCC (PLCC68-P-950) 24.23 [0.954] 24.13 [0.950] 25.27 [0.995] 25.02 [0.985] 1.27 [0.050] 0.53 [0.021] BSC 0.33 [0.013] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 24.23 [0.954] 24.13 [0.950] 25.27 [0.995] ...
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LH540235/45 64TQFP (TQFP-64-P-1414) 16.0 [0.630] 14.0 [0.551] BASIC BASIC 1.60 [0.063] 1.45 [0.057] 1.35 [0.53] MAX. MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 44 2048 x 18/4096 x 18 Synchronous FIFOs DETAIL 0.20 [0.008] 0.09 [0.004] 0.75 [0.030] 0.45 ...
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Synchronous FIFOs ORDERING INFORMATION LH540235/45 X Device Type Package Example: LH540245U-20 (4096 x 18 Sychronous FIFO, 20 ns, 68-pin PLCC Speed 20 25 Cycle Time (ns 68-Pin Plastic Leaded Chip Carrier ...
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LH540235/45 BOLD ITALIC = Enhanced Operating Mode 46 2048 x 18/4096 x 18 Synchronous FIFOs ...