LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 32
LH540235M-20
Manufacturer Part Number
LH540235M-20
Description
2048 x 18 / 4096 x 18 Synchronous FIFOs
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
1.LH540235M-20.pdf
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TIMING DIAGRAMS (cont’d)
LH540235/45
32
Enhanced Operating Mode Timing Diagram
NOTES:
1. t
2. The internal state of the FIFO:
rising WCLK edge for HF to change predictably during the current
clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than t
that HF will change state until the next following WCLK edge.
At
At
At
SKEW1
Q
D
0
0
WCLK
RCLK
A
C
WEN
B
- D
- Q
REN
OE
HF
is the minimum time between a rising RCLK edge and a
, exactly half full.
, half+1 words.
, exactly half full again.
17
17
OUTPUT REGISTER
NO WRITE
LOW
t
ENS
DATA IN
A
Figure 19. Half-Full-Flag Timing, When Synchronized
t
t
ENH
SKEW1
SKEW1
to Input Port (Enhanced Operating Mode)
t
A
1
, then it is not guaranteed
B
t
DS
DATA WRITE
t
HFS
DATA READ
NO WRITE
t
t
ENS
HFS
C
2048 x 18/4096 x 18 Synchronous FIFOs
t
t
SKEW1
ENH
t
A
1
DATA WRITE
DATA READ
NEXT
t
DS
t
HFS
540235-25
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