LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 23

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

TIMING DIAGRAMS (cont’d)
2048 x 18/4096 x 18 Synchronous FIFOs
NOTES:
1. t
2. t
3. EF may be used to determine when the first data word D
WCLK edge for FF to change predictably during the current clock cycle.
If the time between the rising edge of RCLK and the rising edge of
WCLK is less than t
state until the next following WCLK edge.
edge and a rising RCLK edge to assure a correct readout of the first data
word D
If t
one more clock cycle delay at 2 t
timing restrictions apply only when the FIFO has been empty (EF = LOW).
D
SKEW2
FRL
0
FRL
always is available on the next cycle after EF has gone HIGH.
(First-Read Latency) is the minimum time between a rising WCLK
is not met, D
is the minimum time between a rising RCLK edge and a rising
0
in response to the next RCLK edge. Thus, t
Q
D
0
WCLK
0
RCLK
- Q
WEN
- D
REN
OE
EF
17
17
0
SKEW2
may be available either at t
, then it is not guaranteed that FF will change
Reset Operation, With Simultaneous Read and Write
Figure 9. Latency for the First Data Word After a
t
CLK
ENS
t
DS
+ t
VALID WRTE)
D 0 (FIRST
SKEW2
t
SKEW2
. The First-Read Latency
CLK
(1)
+ t
FRL
t
FRL
SKEW2
= t
0
(2)
t
may be read.
CLK
OLZ
D
t
REF
, or after
1
+ t
SKEW2
t
OE
.
t
A
D
(3)
2
D
0
D
t
A
3
D
D
1
4
LH540235/45
540235-8
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