LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 12

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LH540235M-20

Manufacturer Part Number
LH540235M-20
Description
2048 x 18 / 4096 x 18 Synchronous FIFOs
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
LH540235/45
NOTES:
1. q = Programmable-Almost-Empty Offset value. (Default value: q = 127.)
2. p = Programmable-Almost-Full Offset value. (Default value: p = 127.)
3. Only 11 (2048
4. The flag output is delayed by one full clock cycle in Enhanced Operating Mode, when synchronous operation is specified for intermediate flags.
BOLD ITALIC = Enhanced Operating Mode
12
NUMBER OF UNREAD DATA WORDS PRESENT WITHIN FIFO
2048
1025 to (2048 – (p + 1))
(2048 – p) to 2047
(q + 1) to 1024
2048
18 bit should be LOW (zero).
1 to q
2048
0
18 FIFO
18), or all 12 (4096
18), of the 12 offset-value-register bits should be programmed. The unneeded most-significant-end
2049 to (4096 – (p + 1))
(4096 – p) to 4095
(q + 1) to 2048
4096
1 to q
4096
0
18 FIFO
Table 4. Status Flags
1, 2
FLAG
FULL
FF
H
H
H
H
H
L
2048 x 18/4096 x 18 Synchronous FIFOs
PAF
H
H
H
H
L
L
MIDDLE FLAGS
HF
H
H
H
L
L
L
PAE
H
H
H
H
L
L
EMPTY
FLAG
EF
H
H
H
H
H
L

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