LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 3
LH540235M-20
Manufacturer Part Number
LH540235M-20
Description
2048 x 18 / 4096 x 18 Synchronous FIFOs
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
1.LH540235M-20.pdf
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BOLD ITALIC = Enhanced Operating Mode
2048 x 18/4096 x 18 Synchronous FIFOs
eration of two 18-bit FIFOs as one 36-bit FIFO may be
ensured by ‘interlocked’ crosscoupling of the status-
flag outputs from each FIFO to the expansion inputs
of the other one; that is, FF to WXI/WEN
RXI/REN
FIFOs. This ‘interlocked’ operation takes effect
BOLD ITALIC = Enhanced Operating Mode.
In the Enhanced Operating Mode, coordinated op-
2
, in both directions between two paralleled
V
D
D
D
D
D
V
D
D
D
D
D
D
D
D
D
D
CC
14
13
12
11
10
SS
9
8
7
6
5
4
3
2
1
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32
9
8
Figure 2. Pin Connections for PLCC Package
7
6
2
, and EF to
5
4
33 34 35 36 37 38 39 40 41 42 43
3
2
1
automatically, if two paralleled FIFOs are crosscon-
nected in this manner, with the EMODE control input
being asserted (LOW) (see Tables 1 and 2, also Fig-
ures 28 and 31). IDT-compatible depth cascading no
longer is available when operating in this ‘inter-
locked-paralleled’ mode; however, pipelined depth
cascading remains available.
68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
EMODE
V
V
V
V
Q
Q
Q
Q
V
Q
Q
Q
Q
Q
Q
Q
SS
SS
SS
CC
CC
14
13
12
11
10
9
8
7
6
5
4
LH540235/45
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540235-2
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