LH540235M-20 SHARP [Sharp Electrionic Components], LH540235M-20 Datasheet - Page 19

• Manufacturer Part Number: LH540235M-20
• Description: 2048 x 18 / 4096 x 18 Synchronous FIFOs
• Manufacturer: SHARP [Sharp Electrionic Components]

DESCRIPTION OF SIGNALS AND
OPERATING SEQUENCES (cont’d)
BOLD ITALIC = Enhanced Operating Mode
2048 x 18/4096 x 18 Synchronous FIFOs
operation is 127
which does not exceed this total nominal number of words
for the device, as explained in the description of Load
(LD).
no read operations have been performed since the
completion of the reset operation, PAF goes LOW after
(2048-p) write operations for the LH540235, or after
(4096-p) write operations for the LH540245 (see Table 4).
the FIFO is from seven-eighths full to completely full.
from HIGH to LOW only after a LOW-to-HIGH transition
of the Write Clock WCLK, and from LOW to HIGH only
after a LOW-to-HIGH transition of the Read Clock RCLK.
Thus, in this operating mode, PAF behaves as an ‘asyn-
chronous flag.’
hand, PAF gets updated only after a LOW-to-HIGH
transition of the Write Clock WCLK, and thus behaves
as a ‘synchronous flag,’ whenever Control Register
bit 04 is HIGH (see Table 5).
WRITE EXPANSION OUT/HALF-FULL FLAG
(WXO/HF)
operation, it behaves as a Half-Full Flag (HF), in accord-
ance with Table 4. In IDT-compatible ‘cascaded’ opera-
tion, it behaves as a Write Expansion Output (WXO)
signal to coordinate writing operations with the next FIFO
in the cascade. Under these same conditions, also, the
dual-purpose WXI/ WEN
as Write Expansion Input (WXI) and Read Expansion
Input (RXI) signals respectively.
‘cascaded’ to operate as a deeper ‘effective FIFO,’ in an
IDT-style ‘daisy-chain’ ring configuration, the Write Ex-
pansion Input (WXI) of each FIFO is connected to WXO
of the previous FIFO in the ring, with WXI of the ‘first-load’
or ‘master’ FIFO being connected to WXO of the last FIFO
so as to complete the ring. Similar connections are made
for each FIFO in the ring, parallel to these WXO-to-WXI
connections, for Read Expansion Input (RXI) and Read
Expansion Output (RXO/ EF
RXO).
FIFO operating in cascaded mode, a LOW-going pulse is
emitted by that FIFO on its WXO output, and the FIFO is
deactivated for writing at the next valid WCLK; and the
next FIFO in the ring is simultaneously activated for
The default value of ‘p’ after the completion of a reset
If the FIFO has been reset by asserting RS (LOW), and
If p is still at its default value, PAF is LOW whenever
In the IDT-Compatible Operating Mode, PAF changes
In the Enhanced Operating Mode, on the other
WXO/HF is a dual-purpose signal. In ‘standalone’
When two or more LH540235 or LH540245 FIFOs are
When the last physical location has been written in a
10
. However, ‘p’ may be set to any value
2
and RXI/ REN
2
, when it is behaving as
2
inputs behave
writing. Otherwise, WXO remains constantly HIGH when-
ever the FIFO is operating in cascaded mode. This LOW-
going WXO pulse serves as a ‘write token’ in the
‘token-passing’ FIFO-cascading scheme; it is passed on
to the next FIFO in the ring via its WXI input. When this
next FIFO receives the write token, it is activated for
writing at the next valid WCLK.
or ‘master’ FIFO in the ring, and to any and all ‘slave’
FIFOs in the ring. However, WXO has no necessary
function for FIFOs operating in the ‘standalone’ mode.
Consequently, in that mode, the same output pin is used
for HF; it follows that HF is not available as an output from
any FIFO which is operating in the IDT-compatible cas-
caded mode. A FIFO is initialized into ‘cascaded master’
mode, into ‘cascaded slave’ mode, into interlocked-par-
alleled mode , or into standalone mode according to the
state of its WXI/ WEN
inputs during a reset operation, and of EMODE (see
Table 1, Table 2, and Table 5).
HF goes LOW whenever the FIFO is more than half full;
that is, whenever subtracting the value of the FIFO’s
internal read pointer from the value of its internal write
pointer yields a difference which is less than half of the
total nominal number of 18-bit words in the FIFO’s physi-
cal memory, which is 1024 for the LH540235 or 2048 for
the LH540245 respectively (see Table 4). The subtraction
is performed using modular arithmetic, modulo this total
nominal number of words, which is 2048 for the
LH540235 or 4096 for the LH540245 respectively.
it is operating in standalone mode or in interlocked-par-
alleled mode, and no read operations have been per-
formed since the completion of the reset operation, HF
goes LOW after 1025 write operations for the LH540235,
or after 2049 write operations for the LH540245 (see
again Table 4).
from HIGH to LOW only after a LOW-to-HIGH transition
of the Write Clock WCLK, and from LOW to HIGH only
after a LOW-to-HIGH transition of the Read Clock RCLK.
Thus, in this operating mode, HF behaves as an ‘asyn-
chronous flag.’
hand, HF gets updated only after a LOW-to-HIGH
transition of the Read Clock RCLK, or else after a
LOW-to-HIGH transition of the Write Clock WCLK,
according to the setting of bits 03 and 02 of the
Control Register (see Table 5). Thus, in this mode HF
behaves as a ‘synchronous flag,’ and may be syn-
chronized either to the input side of the FIFO (i.e., to
WCLK), or to the output side of the FIFO (i.e., to
RCLK).
The foregoing description applies both to the ‘first-load’
In standalone or interlocked-paralleled operation,
If the FIFO has been reset by asserting RS (LOW), and
In the IDT-Compatible Operating Mode, HF changes
In the Enhanced Operating Mode, on the other
2
, RXI/ REN
2
, and FL/ RT control
LH540235/45
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