SSTUB32866EC/G,518 NXP Semiconductors, SSTUB32866EC/G,518 Datasheet - Page 13

• Manufacturer Part Number: SSTUB32866EC/G,518
• Description: IC REG BUFFER 25BIT 96-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32866EC/G,518

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Package / Case: 96-LFBGA
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Logic Family: SSTU
• Number Of Circuits: 1
• Maximum Clock Frequency: 450 MHz
• Propagation Delay Time: 1.5 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage (max): 2 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3543-2; 935281279518; SSTUB32866EC/G-T

NXP Semiconductors
Table 9.
At recommended operating conditions (see
[1]
[2]
[3]
Table 10.
At recommended operating conditions (see
[1]
[2]
Table 11.
At recommended operating conditions (see
SSTUB32866_4
Product data sheet
Symbol
f
t
t
t
t
t
Symbol
f
t
t
t
t
t
t
t
Symbol
dV/dt_r
dV/dt_f
dV/dt_Δ
clock
W
ACT
INACT
su
h
max
PDM
PD
LH
HL
PDMSS
PHL
PLH
This parameter is not necessarily production tested.
VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t
HIGH.
VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of t
Includes 350 ps of test load transmission line delay.
This parameter is not necessarily production tested.
Parameter
clock frequency
pulse width
differential inputs active time
differential inputs inactive time
set-up time
hold time
Parameter
maximum input clock frequency
peak propagation delay
propagation delay
LOW to HIGH delay
HIGH to LOW delay
simultaneous switching peak
propagation delay
HIGH to LOW propagation delay
LOW to HIGH propagation delay
Timing requirements
Switching characteristics
Data output edge rates
Parameter
rising edge slew rate
falling edge slew rate
absolute difference between dV/dt_r
and dV/dt_f
All information provided in this document is subject to legal disclaimers.
Table
Table
Table
Conditions
CK, CK HIGH or LOW
DCS before CK↑, CK↓, CSR HIGH;
CSR before CK↑, CK↓, DCS HIGH
DCS before CK↑, CK↓, CSR LOW
DODT, DCKE and data (Dn) before CK↑,
CK↓
PAR_IN before CK↑, CK↓
DCS, DODT, DCKE and data (Dn) after
CK↑, CK↓
PAR_IN after CK↑, CK↓
7), unless otherwise specified. See
7), unless otherwise specified. See
7), unless otherwise specified. See
Rev. 04 — 15 April 2010
Conditions
from 20 % to 80 %
from 80 % to 20 %
from 20 % or 80 %
to 80 % or 20 %
Conditions
single bit switching;
from CK↑ and CK↓ to Qn
from CK↑ and CK↓ to PPO
from CK↑ and CK↓ to QERR
from CK↑ and CK↓ to QERR
from CK↑ and CK↓ to Qn
from RESET↓ to Qn↓
from RESET↓ to PPO↓
from RESET↓ to QERR↑
1.8 V DDR2-800 configurable registered buffer with parity
INACT(max)
Section
Section
Section
Min
1
1
-
[1][2]
[1][2]
[1][3]
[1]
after RESET is taken LOW.
Min
450
1.1
0.5
1.2
1
-
-
-
-
SSTUB32866
11.1.
11.1.
11.2.
Min
-
1
-
-
0.6
0.5
0.5
0.5
0.4
0.4
Typ
-
-
-
ACT(max)
Typ
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
after RESET is taken
Max
4
4
1
Max
-
1.5
1.7
3
2.4
1.6
3
3
3
Max
450
-
10
15
-
-
-
-
-
-
V/ns
Unit
V/ns
V/ns
13 of 30
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns