SSTUB32866EC/G,518 NXP Semiconductors, SSTUB32866EC/G,518 Datasheet - Page 19

• Manufacturer Part Number: SSTUB32866EC/G,518
• Description: IC REG BUFFER 25BIT 96-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32866EC/G,518

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Package / Case: 96-LFBGA
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Logic Family: SSTU
• Number Of Circuits: 1
• Maximum Clock Frequency: 450 MHz
• Propagation Delay Time: 1.5 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage (max): 2 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3543-2; 935281279518; SSTUB32866EC/G-T

NXP Semiconductors
SSTUB32866_4
Product data sheet
11.2 Data output slew rate measurement information
V
All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz; Z
Fig 16. Load circuit, HIGH-to-LOW slew measurement
Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement
Fig 18. Load circuit, LOW-to-HIGH slew measurement
Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement
DD
= 1.8 V ± 0.1 V.
(1) C
(1) C
L
L
includes probe and jig capacitance.
includes probe and jig capacitance.
output
All information provided in this document is subject to legal disclaimers.
output
o
= 50 Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified.
Rev. 04 — 15 April 2010
dv_r
1.8 V DDR2-800 configurable registered buffer with parity
dv_f
DUT
DUT
OUT
OUT
C
20 %
L
dt_r
= 10 pF
C
L
(1)
80 %
dt_f
80 %
= 10 pF
(1)
20 %
V
DD
R
test point
test point
R
002aaa377
002aaa379
L
L
= 50 Ω
= 50 Ω
SSTUB32866
002aaa380
002aaa378
V
V
V
V
© NXP B.V. 2010. All rights reserved.
OL
OH
OL
OH
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