SSTUB32866EC/G,518 NXP Semiconductors, SSTUB32866EC/G,518 Datasheet - Page 8

• Manufacturer Part Number: SSTUB32866EC/G,518
• Description: IC REG BUFFER 25BIT 96-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32866EC/G,518

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Package / Case: 96-LFBGA
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Logic Family: SSTU
• Number Of Circuits: 1
• Maximum Clock Frequency: 450 MHz
• Propagation Delay Time: 1.5 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage (max): 2 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3543-2; 935281279518; SSTUB32866EC/G-T

NXP Semiconductors
[3]
7. Functional description
SSTUB32866_4
Product data sheet
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
The SSTUB32866 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity,
designed for 1.7 V to 2.0 V V
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The
control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers
that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18
specifications. The error (QERR) output is 1.8 V open-drain driver.
The SSTUB32866 operates from a differential clock (CK and CK). Data are registered at
the crossing of CK going HIGH, and CK going LOW.
The C0 input controls the pinout configuration for the 1 : 2 pinout from A configuration
(when LOW) to B configuration (when HIGH). The C1 input controls the pinout
configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH).
The SSTUB32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration,
parity is checked on the PAR_IN input which arrives one cycle after the input data to which
it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after
the corresponding data inputs.
When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the
second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which
arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of
the first device. The PPO and QERR signals are produced on the second device three
clock cycles after the corresponding data inputs. The PPO output of the first register is
cascaded to the PAR_IN of the second register. The QERR output of the first register is
left floating and the valid error information is latched on the QERR output of the second
register.
If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock
cycles or until RESET is driven LOW. The DIMM-dependent signals (DCKE, DCS, DODT,
and CSR) are not included in the parity check computation.
The device supports low-power standby operation. When RESET is LOW, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage
(VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and
all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid
logic HIGH or LOW level.
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 15 April 2010
1.8 V DDR2-800 configurable registered buffer with parity
DD
operation.
SSTUB32866
© NXP B.V. 2010. All rights reserved.
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