SSTUB32866EC/G,518 NXP Semiconductors, SSTUB32866EC/G,518 Datasheet - Page 18

• Manufacturer Part Number: SSTUB32866EC/G,518
• Description: IC REG BUFFER 25BIT 96-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of SSTUB32866EC/G,518

• Logic Type: 1:1, 1:2 Configurable Registered Buffer with Parity
• Package / Case: 96-LFBGA
• Supply Voltage: 1.7 V ~ 2 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Logic Family: SSTU
• Number Of Circuits: 1
• Maximum Clock Frequency: 450 MHz
• Propagation Delay Time: 1.5 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage (max): 2 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3543-2; 935281279518; SSTUB32866EC/G-T

NXP Semiconductors
SSTUB32866_4
Product data sheet
Fig 13. Voltage waveforms; set-up and hold times
Fig 14. Voltage waveforms; propagation delay times (clock to output)
Fig 15. Voltage waveforms; propagation delay times (reset to output)
V
V
V
V
t
t
V
V
PLH
PLH
ID
ref
IH
IL
IH
IL
= V
= V
= 600 mV.
= V
= V
= 0.5V
and t
and t
ref
ref
ref
ref
All information provided in this document is subject to legal disclaimers.
− 250 mV (AC voltage levels) for differential inputs. V
PHL
PHL
− 250 mV (AC voltage levels) for differential inputs. V
+ 250 mV (AC voltage levels) for differential inputs. V
+ 250 mV (AC voltage levels) for differential inputs. V
DD
input
.
are the same as t
are the same as t
CK
CK
Rev. 04 — 15 April 2010
output
RESET
output
1.8 V DDR2-800 configurable registered buffer with parity
CK
CK
LVCMOS
V
t
V
PLH
ref
ICR
PD
PD
.
.
t
su
0.5V
V
t
PHL
ICR
DD
t
h
V
t
V
V
PHL
T
ICR
T
002aaa376
IL
IL
IH
IH
002aaa374
V
V
= GND for LVCMOS inputs.
= GND for LVCMOS inputs.
SSTUB32866
V
V
V
V
ref
ID
= V
002aaa375
= V
IH
IL
OH
OL
V
i(p-p)
DD
DD
V
V
OH
OL
for LVCMOS inputs.
for LVCMOS inputs.
V
V
IH
IL
© NXP B.V. 2010. All rights reserved.
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