MAX11040KGUU+T Maxim Integrated, MAX11040KGUU+T Datasheet
MAX11040KGUU+T
Specifications of MAX11040KGUU+T
Related parts for MAX11040KGUU+T
MAX11040KGUU+T Summary of contents
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Simultaneous-Sampling, General Description The MAX11040K/MAX11060 are 24-/16-bit, 4-channel, simultaneous-sampling, sigma-delta analog-to-digital converters (ADCs). The devices allow simultaneous sampling of as many as 32 channels using a built-in cascade feature to synchronize as many as eight devices. The serial ...
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... OUT REFIO = +25°C.) (Note 1) A MIN TYP MAX 24 16 0.1 0.001 0.004 0.006 0.001 - 0.5 1 < 0.025 0.03 103 106 94.5 -94 -90 -106 100 89 100 0.25 0.005 + 0.3V) AVDD = REFIO UNITS Bits LSB %FS mV %FS ppm/°C ppm/° Maxim Integrated ...
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... REFIO Sink Current REFIO Source Current REFIO Input Capacitance CRYSTAL OSCILLATOR (XIN, XOUT) Tested Resonant Frequency Maximum Crystal ESR Oscillator Startup Time Oscillator Stability M axi sci l l ator Load Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs , f = 24.576MHz, f AVDD XIN CLOCK = unless otherwise noted ...
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... DVDD 100 ±0.01 ± DVDD DVDD 30 3.0 3.6 2.7 V AVDD 25 = 0Hz 0 0Hz 0.3 at 1kHz REFIO UNITS μ DVDD V ±1 μ DVDD V kΩ μ μ Maxim Integrated ...
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... AIN_+ and AIN_- input, do not trigger the analog input protection circuitry. Note 10: Test performed using RXD MP35. Note 11: All digital inputs at DGND or DVDD. Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated. Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational. Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs , f = 24.576MHz, f ...
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... FREQUENCY (Hz) RMS AMPLITUDE vs. SOURCE RESISTANCE 100,000 10 100 SOURCE RESISTANCE (Ω REF1 REF2 1 10 100 4000 5000 6000 7000 8000 1000 10,000 100,00 Maxim Integrated ...
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... INPUT FREQUENCY -80 -90 -100 -110 -120 -130 0 500 1000 1500 INPUT FREQUENCY (Hz) GAIN ERROR vs. SUPPLY VOLTAGE 1.0 AVDD = DVDD 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 3.0 3.1 3.2 3.3 3.4 3.5 SUPPLY VOLTAGE (V) Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs = 24.576MHz 16ksps, V OUT REFIO OFFSET ERROR vs. SUPPLY VOLTAGE 0.10 AVDD = DVDD 0.08 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 -0.10 3.0 3.1 3.2 3.3 3.4 2000 SUPPLY VOLTAGE (V) GAIN ERROR vs. TEMPERATURE 1 ...
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... TEMPERATURE (°C) I DVDD 47 76 105 = 2.5V (external REFIO REF0 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE 500 AVDD = DVDD 400 300 200 100 I AVDD 0 76 105 3.0 3.1 3.2 3.3 SUPPLY VOLTAGE (V) CRYSTAL OSCILLATOR STARTUP TIME MAX11040K/11060 toc20 40μs/div = C = REF1 REF2 I DVDD 3.4 3.5 3.6 CLKOUT 500mV/div Maxim Integrated ...
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... Reference Voltage Output/Input. Reference voltage for analog-to-digital conversion. In internal reference 9 REFIO mode, the reference buffer provides a +2.5V nominal output. In external reference mode, overdrive REFIO with an external reference between 2.3V to 2.7V. Bypass REFIO with a 1μF capacitor to AGND. Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs + AIN0- ...
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... XIN and XOUT, CLKOUT provides a buffered version of the internal oscillator’s clock. Setting the XTALEN bit to 0 places CLKOUT in a high-impedance state. 10 Pin Description (continued) FUNCTION ) . The outp 30kΩ i nter nal and Maxim Integrated ...
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... Positive Analog Input Channel 3 34 AIN3- Negative Analog Input Channel 3 36 REF2 ADC2 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND. 37 AIN2+ Positive Analog Input Channel 2 38 AIN2- Negative Analog Input Channel 2 Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs Pin Description (continued) FUNCTION 11 ...
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... XIN clock, the switching frequency is MICROCONTROLLER 3.072MHz. The sampling phase lasts for 120ns. OR DSP Figure 1. Simplified Track/Hold Stage digital supply. The 4-wire AVDD ADC Modulator SAMPLE MAX11040K MAX11060 TRACK AIN_+ C SAMPLE+ HOLD C SAMPLE- AIN_- TRACK R ON AVDD/2 ), the bottom TO ADC R ON Maxim Integrated ...
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... Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs Digital Filter Since the transfer function of a digital filter is repeatable and predictable possible to correct for frequency- dependent attenuation in downstream software. See the Compensating for the Rolloff of the Digital Filter in a Typical FFT Analysis section. The transfer function is ...
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... The specifics of the latency are discussed earlier in the data sheet in the Latency section. Analog Input Overvoltage and Fault Protection . The converter accurately represents any REF . In this case, the digital output is REF Analog Input Overflow Detection and Recovery (OVRFLW) ), OVRFLW asserts after a delay defined by REF . REF Maxim Integrated ...
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... DISCONTINUITY LATENCY LATENCY FAULT OVRFLW Figure 4. High-Frequency Analog Input Overvoltage Detection and Recovery Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs the latency of the converter, the ADC conversion result prematurely jumps to the full-scale value when a fault is detected (see Detection Discontinuity in Figure 4). During a fault condition and the subsequent fault- recovery time, the ADC conversion result remains at full scale ...
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... DRDYOUT are used for daisy chaining multiple devices together. See the Multiple Device Connection section for details on how to connect CASCIN, CASCOUT, FAULT-DETECTION THRESHOLD ( PFT LATENCY FULL SCALE (|0.88V REF RECOVERY TIME LATENCY REF0 REF1 REF2 REF3 REFIO |) NFT |) +2.5V REFERENCE Maxim Integrated ...
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... HIGH-Z DOUT Figure 8. General Write-Operation Timing Diagram Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs ferred MSB first. Drive CS high to disable the interface and place DOUT in a high-impedance state. An interface operation with the devices takes effect on the last rising edge of SCLK goes high before the complete transfer, the write is ignored ...
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... Read Sampling Instant 1 1000000 bits Control Register Write Data-Rate Control 0 1010000 16 bits Register Read Data-Rate Control 1 1010000 16 bits Register Write Configuration 0 1100000 bits Register Read Configuration 1 1100000 bits Register 1 1110000 bits Read Data Register Registers FUNCTION Maxim Integrated ...
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... PDBUF otherwise, PDBUF should be set enable the internal reference buffer. [1:0] Reserved Must set to 0. Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs which is 1.3μs to 333μs with f (see Table 3.) The Configuration register contains 5 bits that control the functionality of the devices. The default state is 0x00. ...
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... Device address tag. IC[2:0] starts with 000 for the device nearest the master. Channel 0 address tag = 00 Channel 1 16-bit conversion result (two’s complement) — Device address tag. IC[2:0] starts with 000 for the device nearest the master. Channel 1 address tag = 01 Channel 2 16-bit conversion result (two’s complement) DESCRIPTION DESCRIPTION DESCRIPTION Maxim Integrated ...
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... The final data rate is derived by dividing the XIN clock frequency by a divider value. The divider value is a function of FSAMPC[2:0] and FSAMPF[10:0]: Data Rate = f XINCLOCK Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs — Device address tag. IC[2:0] starts with 000 for the device nearest the master. ...
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... This causes the period from sample 16 to sample different by this amount DATA AT THE OLD CHANGE DATA RATE DATA RATE ) + (PHI x 1.3μs) + 30μs DOUT is the data output period (inverse of the 16 17 DATA AT THE NEW DATA RATE Maxim Integrated ...
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... Table 9. Examples of Output Data Rate as a Function of FSAMPC[2:0] and FSAMPF[10:0] FSAMPC[2:0] FSAMPF[10:0] 11xxxxxxxxx 10111111111 001 00000000001 00000000000 11xxxxxxxxx 10111111111 010 00000000001 00000000000 11xxxxxxxxx 10111111111 011 00000000001 00000000000 Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs Coarse Cycle FSAMPC Factor 000 4 001 128 010 64 011 32 100 16 101 8 ...
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... FSAMPF OUTPUT DATA PERIOD RESOLUTION (24.576MHz CLOCK CYCLES) 769 768 767 767 385 384 RELATIVE SNR OF 24-BIT ACCURACY OF DATA (dB) 256 DATA POINTS (%) 117 0.04 115 0.05 113 0.06 111 0.08 108 0.11 107 0.13 106 0.14 105 0.16 97 0. RELATIVE ACCURACY OF SINGLE CYCLE AT 60Hz (%) 0.23 0.20 0.17 0.16 0.16 0.16 0.16 0.16 0.28 1.26 Maxim Integrated ...
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... CASCIN DSP OR DRDYIN MICROCONTROLLER XIN Figure 13. Daisy- Chaining Multiple Devices Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs n, which is driven by the CASCOUT of device n-1, allows device n to take over the SPI bus until all expect- ed data is written or read; at this point, device n pulls its CASCOUT output low. Similarly, CASCOUT of device n drives CASCIN of device n+1 ...
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... Figure 14. Configuration Register Read Operation Timing Diagram for Eight Cascaded Devices 26 low and the conversion of the device is complete. In this configuration, DRDYOUT of the last device goes low only when all devices in the chain have their data ready. DEVICE 1 DEVICE 2 DEVICE 3 DEVICE 4 t CSW DEVICE 5 DEVICE 6 DEVICE 7 Maxim Integrated ...
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... DOUT CASCOUT0 (CASCIN0 = 0) CASCOUT1 CASCOUT2 CASCOUT3 CASCOUT4 CASCOUT5 CASCOUT6 CASCOUT7 X = RESERVED Figure 15. Data Rate Controller Register Write Operation Timing Diagram for Eight Cascaded Devices Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs B15 B14 B13 X X B10 HIGH-Z 27 ...
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... The process continues as normal with DRDYOUT event 5 appearing t NOTE: THE LATENCY IS NOT TO SCALE MEASURE PAUSE . The effect of a SYNC falling edge S after DRDYOUT event 2. S after DRDYOUT event 4. S DELAY 2 CYCLES Maxim Integrated ...
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... REFIO The serial interface, logic, digital filter, and modulator circuits reset to zero at power-up. The power-on reset circuit releases this reset no more than 1ms after V rises above 2V. DVDD Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs 011...111 000...011 000...010 000...001 000 ...
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... FAULT OVRFLW DOUT XOUT CLKOUT XIN CASCADE DEVICES Synchronizing Multiple Devices to an Independent Clock Source SYNC CS SCLK DIN MAX11040K MAX11040K MAX11060 MAX11060 CASCOUT CASCIN DRDYOUT DRDYIN DEVICE n DEVICE n+1 FAULT OVRFLW DOUT XOUT XIN XOUT DRDYOUT FAULT OVRFLW DOUT Maxim Integrated ...
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... AIN_ DRDYOUT SYNC RECONSTRUCTED DIGITAL OUTPUT Figure 19. Example of Discontinuity in Reconstructed Digital Output Due to SYNC Falling Edge with a Large DRDYOUT-to-SYNC Delay Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs Example: Assume f devices in the chain. Device 1 has the longest t therefore the worst-case SYNC error. ...
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... FFT result. the desired frequencies. (Again, the result is likely to correlate with the time domain array that is loaded into an FFT algorithm.) the Digital Filter section. Fill the rest of the array with zeros. response of the devices’ built-in FIR filter. Analog Filtering Maxim Integrated ...
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... Ensure that digital and analog signal lines are kept sepa- rate. Do not run digital (especially the SCLK and DOUT) lines parallel to any analog lines or under the devices. Maxim Integrated MAX11040K/MAX11060 Cascadable, Sigma-Delta ADCs Lay out the traces in perpendicular directions when a digital line and an analog line cross each other. Bypass AVDD to the analog ground plane with a 0.1μ ...
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... RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE PACKAGE OUTLINE TYPE CODE 38 TSSOP U38+3 LAND PATTERN NO. NO. 90-0140 21-0081 Maxim Integrated ...
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... Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed ...