MAX11040KGUU+T Maxim Integrated, MAX11040KGUU+T Datasheet - Page 28

• Manufacturer Part Number: MAX11040KGUU+T
• Description: Analog to Digital Converters - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt
• Manufacturer: Maxim Integrated

Specifications of MAX11040KGUU+T

• Rohs: yes
• Number Of Channels: 4
• Architecture: Sigma-Delta
• Conversion Rate: 64 KSPs
• Resolution: 24 bit
• Input Type: Differential
• Snr: 106 dB, 117 dB
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 3.6 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1096 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 4
• Voltage Reference: Internal 2.2 V

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
The SYNC input permits multiple devices to sample
simultaneously. The mismatch between the power-up
reset of multiple devices causes the devices to begin
conversion at different times. After a falling edge on the
SYNC input, the device completes the current conver-
sion and then synchronizes subsequent conversions
(see Figure 16).
Upon a SYNC falling edge, the devices measure the time
between the SYNC falling edge to the preceding DRDY-
OUT falling edge, wait until the next DRDYOUT falling
edge, then pause the ADC for the measured amount of
time. Figure 16 shows an example where the converter
is regularly sampling the input and producing a DRDY-
MAX11040K/MAX11060
Figure 16. Effect of a SYNC Falling Edge
28
DRDYOUT
SYNC
AIN_
XIN
1
Sampling with Multiple Devices
t
S
2
S S Y Y N N C C for Simultaneous
t
S
1
t
3
S
NOTE: THE LATENCY IS NOT TO SCALE.
MEASURE
t
S
2
4
t
S
OUT with a period t
as shown in Figure 16 is described in sequence below:
1) A SYNC falling edge is issued two XIN clock cycles
2) The converter remembers the two XIN clock cycles,
3) Then, the converter pauses for the remembered time
4) Correspondingly, DRDYOUT event 4 is issued two
5) The process continues as normal with DRDYOUT
after the DRDYOUT event 2.
and completes the current sample, issuing DRDYOUT
event 3 a period of t
period, two XIN clock cycles for this example.
XIN cycles later than it would have without the
SYNC falling edge.
event 5 appearing t
t
S
PAUSE
3
DELAY 2
t
CYCLES
S
t
5
S
S
. The effect of a SYNC falling edge
t
S
S
S
4
after DRDYOUT event 2.
after DRDYOUT event 4.
t
S
6
5
Maxim Integrated