MAX11040KGUU+T Maxim Integrated, MAX11040KGUU+T Datasheet - Page 21

• Manufacturer Part Number: MAX11040KGUU+T
• Description: Analog to Digital Converters - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt
• Manufacturer: Maxim Integrated

Specifications of MAX11040KGUU+T

• Rohs: yes
• Number Of Channels: 4
• Architecture: Sigma-Delta
• Conversion Rate: 64 KSPs
• Resolution: 24 bit
• Input Type: Differential
• Snr: 106 dB, 117 dB
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 3.6 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1096 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 4
• Voltage Reference: Internal 2.2 V

Table 7. Data Register (MAX11060) (continued)
The Data Rate Control register controls the output data
period, which corresponds to the output data rate of
the ADC. The data period is controlled by both a
coarse (FSAMPC[2:0]) and a fine (FSAMPF[10:0])
adjustment (see Table 8).
The final data rate is derived by dividing the XIN clock
frequency by a divider value. The divider value is a
function of FSAMPC[2:0] and FSAMPF[10:0]:
Figure 11. 192-Bit Data Read Operation Diagram for Two Cascaded Devices
Maxim Integrated
(CASCIN0 = 0)
(DRDYIN0 = 0)
[31:29]
[28:26]
[25:24]
[23:8]
[7:5]
[4:2]
[1:0]
BIT
CASCOUT0
CASCOUT1
DRDYOUT0
DRDYOUT1
DOUT
SCLK
DIN
CS
Data Rate = f
CH3DATA[15:0]
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
NAME
IC[2:0]
IC[2:0]
000
000
10
11
DEVICE 0 DATA READY
CHANNEL 0
24 CYCLES
DEVICE 0 AND DEVICE 1 DATA READY
DEVICE 0
XINCLOCK
Data Rate Control Register
—
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 2 address tag = 10
Channel 3 16-bit conversion result (two’s complement)
—
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 3 address tag = 11
CHANNEL 1
24 CYCLES
DEVICE 0
/Divider
DEVICE 1 TAKES OVER SPI BUS
CHANNEL 2
24 CYCLES
DEVICE 0
Cascadable, Sigma-Delta ADCs
CHANNEL 3
24 CYCLES
DEVICE 0
MAX11040K/MAX11060
Note: Fractional results for the divider are rounded
down to the nearest integer. Coarse cycle factor and
fine cycle factor come from Table 8. The effect of
FSAMPF[10:0] in the formula has limitations as noted in
the table.
Examples of output data rate vs. FSAMPC[2:0] and
FSAMPF[10:0] are shown in Table 9. Table 10 shows
typical device performance for various data rate settings.
Divider = Coarse Cycle Factor x 384 + Fine Cycle
CHANNEL 0
24 CYCLES
DESCRIPTION
DEVICE 1
Factor x FSAMPF[10:0]
24 CYCLES
CHANNEL 1
DEVICE 1
24 CYCLES
CHANNEL 2
DEVICE 1
24 CYCLES
CHANNEL 3
DEVICE 1
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