MAX11040KGUU+T Maxim Integrated, MAX11040KGUU+T Datasheet - Page 20

• Manufacturer Part Number: MAX11040KGUU+T
• Description: Analog to Digital Converters - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt
• Manufacturer: Maxim Integrated

Specifications of MAX11040KGUU+T

• Rohs: yes
• Number Of Channels: 4
• Architecture: Sigma-Delta
• Conversion Rate: 64 KSPs
• Resolution: 24 bit
• Input Type: Differential
• Snr: 106 dB, 117 dB
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 3.6 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1096 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 4
• Voltage Reference: Internal 2.2 V

Table 5. Data Register (EN24BIT = 0) (MAX11040K)
Table 6. Data Register (EN24BIT = 1) (MAX11040K)
Table 7. Data Register (MAX11060)
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
The Data register contains the results of the ADC con-
version. The result is reported in two’s complement for-
mat. The register contains one or two pieces of
information, depending on the state of EN24BIT in the
Configuration register. When EN24BIT is set to zero, the
Data register contains the ADC data truncated to 19
bits, followed by the device and channel addresses
(see Table 5). When EN24BIT is set to one, the data
MAX11040K/MAX11060
20
[95:77]
[76:74]
[73:72]
[71:53]
[52:50]
[49:48]
[47:29]
[28:26]
[25:24]
[95:72]
[71:48]
[47:24]
[23:5]
[23:0]
[95:80]
[79:77]
[76:74]
[73:72]
[71:56]
[55:53]
[52:50]
[49:48]
[47:32]
[4:2]
[1:0]
BIT
BIT
BIT
CH0DATA[18:0]
CH1DATA[18:0]
CH2DATA[18:0]
CH3DATA[18:0]
CH0DATA[23:0]
CH1DATA[23:0]
CH2DATA[23:0]
CH3DATA[23:0]
CH0DATA[15:0]
CH1DATA[15:0]
CH2DATA[15:0]
IC[2:0]
IC[2:0]
IC[2:0]
IC[2:0]
NAME
NAME
00
01
10
11
NAME
IC[2:0]
IC[2:0]
000
000
00
01
Channel 0 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 0 address tag = 00
Channel 1 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 1 address tag = 01
Channel 2 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 2 address tag = 10
Channel 3 19-bit conversion result (two’s complement)
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 3 address tag = 11
Channel 0 24-bit conversion result (two’s complement)
Channel 1 24-bit conversion result (two’s complement)
Channel 2 24-bit conversion result (two’s complement)
Channel 3 24-bit conversion result (two’s complement)
Channel 0 16-bit conversion result (two’s complement)
—
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 0 address tag = 00
Channel 1 16-bit conversion result (two’s complement)
—
Device address tag. IC[2:0] starts with 000 for the device nearest the master.
Channel 1 address tag = 01
Channel 2 16-bit conversion result (two’s complement)
Data Register
contained in the Data register represents the 24-bit
conversion (see Table 6). The data length of the Data
register is 96 bits for each cascaded device. Figure 11
shows the sequence of the conversion result output of
all channels for two cascaded devices. Table 7 is the
data register for the MAX11060.
If the results are not read back prior to completion of
the next conversion, the data is overwritten.
DESCRIPTION
DESCRIPTION
DESCRIPTION
Maxim Integrated