MAX11040KGUU+T Maxim Integrated, MAX11040KGUU+T Datasheet - Page 22

• Manufacturer Part Number: MAX11040KGUU+T
• Description: Analog to Digital Converters - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt
• Manufacturer: Maxim Integrated

Specifications of MAX11040KGUU+T

• Rohs: yes
• Number Of Channels: 4
• Architecture: Sigma-Delta
• Conversion Rate: 64 KSPs
• Resolution: 24 bit
• Input Type: Differential
• Snr: 106 dB, 117 dB
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 3.6 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1096 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 4
• Voltage Reference: Internal 2.2 V

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
The data length of the Data-Rate Control register is 16
bits total for writes and reads (see Table 2). Changes to
the Data-Rate Control register take effect after 16 con-
version periods (Figure 12), i.e., the ADC continues to
operate at the old data rate for another 16 periods. Also,
the last sample at the old data rate (sample 16 in Figure
12) may contain some noise component and should be
discarded. Changes in data rate should be limited to
±5% for correct operation. The data rate register should
not be updated more than once every 32 data rate peri-
ods.
Note: Write to the data rate register in the time window of
10ns after the rising edge of DRDYOUT and 100ns
before the falling edge of DRDYOUT.
The digital filter determines the latency. Latency is
defined as the time between the effective point in time
that a sample is taken and when the resulting digital data
MAX11040K/MAX11060
Figure 12. Timing Diagram for a Data-Rate Change
22
DRDYOUT
CS
DATA READ
CHANGE DATA RATE
1
2
is available for reading (DRDYOUT goes low). The laten-
cy of the converter is specified by the following equation:
where t
programmed sample rate) determined by XINCLOCK
and the selected output data rate, and PHI is the pro-
grammed sampling instant delay for the channel in ques-
tion (0 ≤ PHI ≤ 255). The latency is approximately 405μs
at 16ksps.
Because the two filters operate at different output data
rates, a skew builds up between them over the 16 sam-
ples that both are in operation. For example, at 30ksps,
the minimum data rate step size is 0.125%; so over 16
samples, the difference becomes 2%. This causes the
period from sample 16 to sample 17 to be different by
this amount.
DATA AT THE OLD
DATA RATE
Latency = (6 x t
DOUT
15
is the data output period (inverse of the
16
DOUT
17
) + (PHI x 1.3μs) + 30μs
DATA AT THE NEW
DATA RATE
Maxim Integrated