MAX11040KGUU+T Maxim Integrated, MAX11040KGUU+T Datasheet - Page 30

• Manufacturer Part Number: MAX11040KGUU+T
• Description: Analog to Digital Converters - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt
• Manufacturer: Maxim Integrated

Specifications of MAX11040KGUU+T

• Rohs: yes
• Number Of Channels: 4
• Architecture: Sigma-Delta
• Conversion Rate: 64 KSPs
• Resolution: 24 bit
• Input Type: Differential
• Snr: 106 dB, 117 dB
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 3.6 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1096 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 4
• Voltage Reference: Internal 2.2 V

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
To synchronize multiple devices sharing a single XIN
clock source, transition the SYNC input that is shared
by all devices high to low. When an external sync
source is not available, connect DRDYOUT of the last
device to the SYNC input of all devices in the chain.
The devices ignore any SYNC transitions applied dur-
ing the power-on reset.
If it is undesirable to connect the XIN clock sources
together, due to EMI or other reasons; use DRDYIN,
DRDYOUT, and SYNC to align the conversion timing as
shown in Figure 18. This minimizes the effects of drift
MAX11040K/MAX11060
Figure 18. One Crystal per Device and All SYNC Inputs Driven by DRDYOUT of the Last Device in the Chain
30
MICROCONTROLLER
DSP OR
Multiple Device Synchronization
Using Independent XIN Clock Sources
Applications Information
Using a Shared XIN Clock Source
Synchronizing Multiple Devices
Synchronizing Multiple Devices
SYNC
CS
SCLK
DIN
CASCIN
DRDYIN
XIN
MAX11040K
MAX11060
DEVICE 0
XOUT CLKOUT
CASCOUT
DRDYOUT
OVRFLW
FAULT
DOUT
CASCADE UP TO 8 DEVICES
between the clock sources by resynchronizing after
each conversion when DRDYOUT transitions low. In
this configuration, the maximum correction caused by a
SYNC edge is one XIN clock cycle.
The resulting sampling rate is determined by the sampling
frequency of the device with the slowest clock source,
plus the delay through the DRDYIN to DRDYOUT chain
between this slowest device and the end of the chain.
To periodically synchronize multiple devices to an inde-
pendent timing source, connect the timing source to
the SYNC inputs of the devices. If minimal jitter is
important in the application, program the devices to a
frequency slightly slower than the external frequency,
such that SYNC falling edges only occur a short time
after the DRDYOUT signals.
SYNC
CS
SCLK
DIN
CASCIN
DRDYIN
XIN
MAX11040K
MAX11060
DEVICE n
XOUT
CASCOUT
DRDYOUT
OVRFLW
FAULT
DOUT
to an Independent Clock Source
Synchronizing Multiple Devices
SYNC
CS
SCLK
DIN
CASCIN
DRDYIN
XIN
MAX11040K
MAX11060
DEVICE n+1
XOUT
DRDYOUT
OVRFLW
FAULT
DOUT
Maxim Integrated