MAX11040KGUU+T Maxim Integrated, MAX11040KGUU+T Datasheet - Page 5

• Manufacturer Part Number: MAX11040KGUU+T
• Description: Analog to Digital Converters - ADC 24Bit 4Ch Simul-Samp Cascadable Sig Delt
• Manufacturer: Maxim Integrated

Specifications of MAX11040KGUU+T

• Rohs: yes
• Number Of Channels: 4
• Architecture: Sigma-Delta
• Conversion Rate: 64 KSPs
• Resolution: 24 bit
• Input Type: Differential
• Snr: 106 dB, 117 dB
• Interface Type: 4-Wire (SPI, Microwire), QSPI
• Operating Supply Voltage: 2.7 V to 3.6 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1096 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 4
• Voltage Reference: Internal 2.2 V

ELECTRICAL CHARACTERISTICS (continued)
(V
C
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at V
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
Note 8: Latency is a function of the sampling rate and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
Maxim Integrated
SCLK Rise to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
CASCIN-to-SCLK Rise Setup
SCLK Rise to CASCOUT Valid
SYNC Pulse Width
XIN Clock Pulse Width
DRDYIN to DRDYOUT
XIN Clock to DRDYOUT Delay
XIN Clock Period
XIN Clock to SYNC Setup
SYNC to XIN Clock Hold
XIN-to-CLKOUT Delay
Power-On Reset Delay
REF0
AVDD
= C
= +3.0V to +3.6V, V
removed.
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
REF1
PARAMETER
= C
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
REF2
AVDD
= C
= V
REF3
DVDD
DVDD
= 1μF to AGND, T
= +2.7V to V
= +3.0V.
SYMBOL
t
t
XDRDY
t
t
t
t
t
t
DRDY
t
t
DOE
DOD
CSW
XPW
DOT
t
COT
SYN
t
XCD
t
t
SC
XP
SS
HS
AVDD
A
= T
, f
C
C
C
C
C
C
DRDYIN = DGND
(Note 12)
(Note 12)
(Note 13)
XIN CLOCK
MIN
Cascadable, Sigma-Delta ADCs
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
to T
= 30pF
= 100pF
= 30pF
= 30pF
= 100pF
= 30pF
MAX
CONDITIONS
= 24.576MHz, f
, unless otherwise noted. Typical values are at T
MAX11040K/MAX11060
OUT
= 16ksps, V
MIN
1.5
0.3
0.7
16
16
16
40
16
2
5
REFIO
= +2.5V (external), C
< 16
TYP
< 1
10
A
MAX
= +25°C.) (Note 1)
16
20
16
20
20
40
40
Cycles
UNITS
Clock
REFIO
XIN
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
=
5