ATAES132-SH-EQ-T Atmel, ATAES132-SH-EQ-T Datasheet - Page 133

• Manufacturer Part Number: ATAES132-SH-EQ-T
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-SH-EQ-T

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: SPI
• Factory Pack Quantity: 4000

K.3.2. Write Enable Command (WREN):
Table K-37. SPI instruction set for the Atmel ATAES132
If the ATAES132 receives an invalid instruction code or an invalid memory address, then no response will be sent – the SO
output will remain in the high impedance state. When any error occurs, the EERR bit of the STATUS register is set to 1b to
indicate an error. The host can read the error code from the response memory buffer at address 0xFE00 using the READ
command. Reading the response memory buffer does not reset the error code or change the STATUS.
The device will power up in the write disable state when V
preceded by a write enable instruction. It is not necessary to send the write enable instruction prior to sending command
packets to the command memory buffer.
Figure K-11. SPI write enable (WREN) timing
SCK
Instruction name
WRITE
READ
WRDI
RDSR
WREN
SO
CS
SI
Instruction code
0000 0010 b
0000 0011 b
0000 0100 b
0000 0101 b
0000 0110 b
Operation
Write data to memory
Read data from memory
Reset write enable register
Read status register
Set write enable latch
WREN OP-CODE
CC
HI-Z
is applied. All EEPROM write instructions must therefore be
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
133