ATAES132-SH-EQ-T Atmel, ATAES132-SH-EQ-T Datasheet - Page 87

• Manufacturer Part Number: ATAES132-SH-EQ-T
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-SH-EQ-T

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: SPI
• Factory Pack Quantity: 4000

E.2.14. PermConfig Register
E.2.15. I
E.2.16. ChipConfig Register
PermConfig is a one byte read-only register that is programmed by Atmel at the factory. This register cannot be changed by
the customer. The default value 0x01 enables all cryptographic commands.
Table E-10. PermConfig register definition
If the EncryptE bit is 1b, then the encrypt, decrypt and legacy command availability is determined by the ChipConfig.EncDecrE
and ChipConfig.LegacyE bits. If the EncryptE bit is 0b, then the encrypt, decrypt, and legacy commands are disabled. See
the ChipConfig register definition in Section E.2.16 for additional information.
I
the standard I
definition in Section E.2.11).
Table E-11. I
Bit 0 selects the serial interface mode; 0b selects SPI interface mode, while 1b selects I
the contents of bits 1 to 7 are ignored.
The default value of the I
Address is 0xA0) for catalog numbers with an I
interface configuration. See Appendix J for the I
specifications.
ChipConfig is a one byte register that controls device level functionality of the ATAES132. The customer can write the
ChipConfig register with the standard I
LockConfig register definition in Section E.2.11).
Table E-12. ChipConfig register definition
If the ChipConfig.LegacyE bit is 1b, then the legacy command (Section 7.18) is enabled. If ChipConfig.LegacyE is 0b, then a
parse error ReturnCode will be returned in response to a legacy command. If the ChipConfig.EncDecrE bit is 1b, then the
encrypt command (Section 7.10) and decrypt command (Section 7.8) are enabled. If ChipConfig.EncDecrE is 0b, then a parse
error ReturnCode will be returned in response to an encrypt command or decrypt command.
The default configuration of the PermConfig register allows the customer to control the availability of the encrypt, decrypt, and
legacy commands using the ChipConfig register. However, the ChipConfig.EncDecrE bit and ChipConfig.LegacyE bit will be
ignored if the ATAES132 is configured at the factory to disable external encryption (see the PermConfig Register definition in
Section E.2.14).
2
2
CAddr is a one byte register that controls the ATAES132 serial interface. The customer can write the I
CAddr Register
Bit 7
Bit 7
Bit 7
PowerUpState
2
2
C or SPI write commands unless the configuration memory has been locked (see the LockConfig register
CAddr register definition
Bit 6
Bit 6
Bit 6
2
CAddr register depends on the ordering code (see Appendix Q); I
Bit 5
Bit 5
Bit 5
2
C or SPI write commands unless the configuration memory has been locked (see the
Reserved for future use
I
2
C device address
2
C interface configuration, I
2
C interface specifications. See Appendix K for the SPI interface
Reserved for future use
Bit 4
Bit 4
Bit 4
Bit 3
Bit 3
Bit 3
Atmel ATAES132 Preliminary Datasheet
2
CAddr is 0x00 for catalog numbers with a SPI
Bit 2
Bit 2
Bit 2
2
C interface mode. If bit 0 is 0b, then
2
CAddr is 0xA1 (I
EncDecrE
Bit 1
Bit 1
Bit 1
8760A−CRYPTO−5/11
2
CAddr register with
2
C Device
EncryptE
LegacyE
SPI/I
Bit 0
Bit 0
Bit 0
2
C
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