ATAES132-SH-EQ-T Atmel, ATAES132-SH-EQ-T Datasheet - Page 59

• Manufacturer Part Number: ATAES132-SH-EQ-T
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-SH-EQ-T

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: SPI
• Factory Pack Quantity: 4000

Table 7-61. Input parameters
Note:
Table 7-62. Output parameters
The command and response packet is transmitted as a block beginning with the count and ending with a packet checksum.
This block format is described in Section 6.1.
Opcode
Mode
Param1
Param2
Data
Name
ReturnCode
Random
1.
The RNG seed register in the EEPROM will be updated automatically if mode bit 1 = 0b unless the seed register
was previously updated after the most recent power on reset, wake from the sleep state, reset command, or
tamper event. Updating the RNG seed register increases the randomness of the nonce, however, the EEPROM
write endurance specification must be respected.
(Bytes)
0 or 16
Name
Nonce
Mode
Zero
Zero
InSeed
Size
1
Notes
Upon success, 0x00 will be returned. Any command execution failure or validation failure
generates a non-zero error code, per Section 6.3.
In random nonce mode, the random number used to generate the nonce is returned. In
inbound nonce mode, no data is returned.
(Bytes)
Size
12
1
1
2
2
Notes
0x01
Bit 0: If 1b, generate a random nonce using the RNG
Bit 1: If 0b, update the EEPROM RNG seed prior to nonce generation
Bits 2-7: Reserved. Must be 0b
Always 0x0000
Always 0x0000
Input seed (required)
If 0b, use the InSeed as the nonce (Inbound nonce mode), mode bit 1
is ignored
If 1b, generate a random nonce using the existing RNG seed
Atmel ATAES132 Preliminary Datasheet
8760A−CRYPTO−5/11
(1)
59