ATAES132-SH-EQ-T Atmel, ATAES132-SH-EQ-T Datasheet - Page 161

• Manufacturer Part Number: ATAES132-SH-EQ-T
• Description: EEPROM AES 32Kbit EE SPI
• Manufacturer: Atmel

Specifications of ATAES132-SH-EQ-T

• Rohs: yes
• Maximum Clock Frequency: 10 MHz
• Operating Supply Voltage: 6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Interface Type: SPI
• Factory Pack Quantity: 4000

Appendix R. Errata
R.1.
R.1.1. Memory Contents
R.1.2. Configuration Memory Map Change
R.1.3. SPI Write Output State
R.1.4. SPI Configuration Memory Write Error not Flagged
First Silicon Errata (INFO DeviceNum = 0x0A01 or 0x0A02)
Pre-production version is not suitable for qualification. First silicon is not fully tested and may not meet all of the parametric
specifications listed in Section 9.
EEPROM contents are not identical to the production configuration described in Appendix O. This is intentional. The first
silicon can be easily distinguished from later revisions.
The ManufacturingID register and PermConfig register location in first silicon are different than in later revisions. In later
revisions the PermConfig register is at address 0xF02D, and the ManufacturingID register is at address 0xF02B to 0xF02C.
The TempCal register did not exist in first silicon. The TempOffset register was two bytes in first silicon, but was expanded to
accommodate improved temperature sensor calibration procedures.
Table R-51. Partial configuration memory map for the Atmel ATAES132 first silicon
The SO output pin should always be in the high impedance state during an SPI Write operation. Actual behavior is the SO pin
is in the high impedance state if no errors are detected in the command packet; however, if the packet contains an error, then
SO may be forced high when the error is detected. SO will remain high until the entire write command packet is clocked in
and the
This problem will be fixed in future revisions of ATAES132.
If an SPI write to the configuration memory is attempted while the device is in the write disable state then the EEPROM write
will fail (as expected). The EERR bit of the STATUS register should be set to 1b to indicate an error. Actual behavior is the
EEPROM does not write and the EERR status bit is 0b (erroneously indicating that no error occurred).
This problem will be fixed in future revisions of ATAES132.
Address
F000
F008
F010
F018
F020
F028
F030
F038
F040
F048
h
h
h
h
h
h
h
h
h
h
-F007
-F00F
-F017
-F01F
-F027
-F02F
-F037
-F03F
-F047
-F04F
input goes high.
h
h
h
h
h
h
h
h
h
h
LockKeys
EncRead
I
2
0
CAddr
h
/ 8
h
Jedec
EncWrtSiz
LockSmall
ChipConfi
1
h
/ 9
h
DeviceNum
LockConfig
2
h
ManufacturingID
/ A
TempOffset
h
3
h
/ B
SerialNum
LotHistory
Reserved
h
RFU
Atmel ATAES132 Preliminary Datasheet
PermConfi
4
h
/ C
h
Reserved
Reserved
5
h
/ D
h
Algorithm
RFU
8760A−CRYPTO−5/11
6
h
/ E
h
EEPage
7
h
/ F
h
161