CY7C09569V-100AC Cypress Semiconductor Corp, CY7C09569V-100AC Datasheet

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... FLEx36™ Synchronous Dual-Port Static RAM Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — 16K x 36 organization (CY7C09569V) — 32K x 36 organization (CY7C09579V) • 0.25-micron CMOS for optimum speed/power • Three modes — Flow-Through — ...

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... Functional Description The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Regis- ters on control, address, and data lines allow for minimal set- up and hold times ...

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... I/O25L 35 I/O24L 36 Notes: 2. This pin is A14L for CY7C09579V. 3. This pin is A14R for CY7C09579V. Document #: 38-06054 Rev. *A 144-Pin Thin Quad Flatpack (TQFP) Top View CY7C09569V (16K x 36) CY7C09579V (32K x 36) CY7C09569V CY7C09579V 108 I/O33R I/O34R 107 106 I/O35R 105 A0R 104 A1R ...

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... CEL CLKL ADSL CNTRSTL I/O26L I/O25L I/O19L VSS VSS I/O19R I/O25R I/O26R NC I/O7L I/O2L I/O2R I/O7R I/O6L I/O5L I/O3L I/O0L I/O0R VSS I/O4L VDD I/O1L I/O1R CY7C09569V CY7C09579V I/O30R I/O32R A0R NC I/O27R I/O31R A1R A5R NC SIZE A7R A6R VDD CER VSS ...

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... Select Pins for Bus Matching. See Bus Matching for details. BM, SIZE Big Endian Pin. See Bus Matching for details Ground Input Power Input. DD Document #: 38-06054 Rev. *A CY7C09569V CY7C09579V -100 100 5 250 Description –A for 16K, A –A for 32K devices CY7C09569V CY7C09579V CY7C09569V CY7C09569V CY7C09579V CY7C09579V -83 - 240 230 MAX Page ...

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... Industrial Commercial 0.01 Industrial Commercial 150 Industrial Description Test Conditions MHz 3.3V DD CY7C09569V CY7C09579V Ambient Temperature +70 C 3.3V – +85 C 3.3V CY7C09569V CY7C09579V -83 -67 2.4 2.4 0.4 0.4 2.0 2.0 0.8 0.8 10 –10 10 –10 385 240 360 230 270 385 75 25 ...

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... Normal Load (Load 1) ALL INPUT PULSES Notes: 6. External AC Test Load Capacitance = 10 pF. 7. (Internal I/O pad Capacitance = 10 pF Test Load. Document #: 38-06054 Rev 1.5V TH (b) Three-State Delay (Load 2) 3.0V 90 100 200 Capacitance (pF) (b) Load Derating Curve CY7C09569V CY7C09579V 3. 590 OUTPUT 435 90% 10 Page ...

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... CY7C09569V CY7C09579V -67 Min. Max. Unit 40 MHz 67 MHz 8.5 ns 8.5 ns 6 ...

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... Switching Characteristics Over the Operating Range (continued) Parameter Description Port to Port Delays t Write Port Clock HIGH to Read Data Delay CWDD t Clock to Clock Set-Up Time CCS Document #: 38-06054 Rev. *A CY7C09569V CY7C09579V -100 -83 Min. Max. Min. Max CY7C09569V CY7C09579V -67 Min. Max. Unit Page ...

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... CD1 Q n [10, 11, 12, 13 CYC2 t CL2 n+1 t CD2 CKLZ . IH following the next rising edge of the clock. IH constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09569V CY7C09579V n+2 n+3 t CKHZ Q Q n+1 n OHZ OLZ n+2 n+3 ...

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... IL t CL1 n 1st Cycle [10, 12, 14, 15, 16 CL2 n CD2 t CLKZ 1st Cycle only required when reading or writing the first Byte or Word). IL CY7C09569V CY7C09579V A n n+1 1st 2nd Cycle Cycle n+1 t CD2 CD2 2nd Cycle 1st Cycle Q n+1 2nd Cycle Q n Page ...

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... Document #: 38-06054 Rev. *A CL2 CD2 HC CD2 [18, 19, 20, 21, 22 MATCH CD1 CWDD , CNTRST = CNTRST for the left port, which is being written to. IH CY7C09569V CY7C09579V CD2 CKHZ CKLZ CD2 CKHZ CKLZ NO NO MATCH t CD1 VALID >maximum specified, then data is not CWDD CCS CKHZ CD2 Q 4 ...

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... CE = ADS = CNTEN = V ; CNTRST = 25. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06054 Rev. *A [13, 23, 24, 25 n+1 n CD2 CKHZ Q n READ NO OPERATION . CY7C09569V CY7C09579V n+2 n n+2 t CKLZ WRITE READ n+4 t CD2 Q n+3 Page ...

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... Switching Waveforms (continued) Pipelined Read-to-Write-to-Read (OE Controlled) t CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT OE Document #: 38-06054 Rev. *A [11, 23, 24, 25 n+1 n+2 n n+2 n+3 t CD2 OHZ READ WRITE CY7C09569V CY7C09579V A A n+4 n CKLZ CD2 Q n+4 READ Page ...

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... Word CKHZ t CD2 2nd Word 1st Word D D n+2 n WRITE READ Operation 1st Cycle 2nd Cycle 2nd Cycle CY7C09569V CY7C09579V n+3 n+3 n+4 t 1st Word CKLZ Q n+3 t CD2 t DC WRITE READ READ READ 1st Cycle 2nd Cycle A n+4 2nd Word ...

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... OUT OE Document #: 38-06054 Rev. *A [11, 13, 14, 15, 24, 25 n+1 n CD1 CKHZ NO READ OPERATION [11 , 13, 23, 24, 25 n OHZ READ CY7C09569V CY7C09579V n+2 n n+2 t CD1 Q n CKLZ DC WRITE READ A A n+3 n CD1 CKLZ DC WRITE READ A n+4 t CD1 A n+5 t CD1 n+4 ...

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... n+1 n+1 n n+1 n+1 t CD1 2nd Word 1st Word t CKHZ Q n 2nd Word READ No WRITE Operation 1st Cycle CY7C09569V CY7C09579V n+1 n CD1 CD1 CKLZ WRITE READ READ 2nd Cycle 1st Cycle 2nd Cycle Page n+2 n+1 ...

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... Note: 27 R/W = CNTRST = Document #: 38-06054 Rev. *A [27] t SAD t SCN t CD2 READ WITH COUNTER [27 n+1 READ WITH COUNTER CY7C09569V CY7C09579V t HAD t HCN Q n+1 n+2 COUNTER HOLD READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+2 n+3 COUNTER HOLD t READ DC WITH ...

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... CE R CNTRST = V IL 29. The “Internal Address” is equal to the “External Address” when ADS = CNTEN = V Document #: 38-06054 Rev n n+1 n+1 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and CNTRST=V IL CY7C09569V CY7C09579V [28, 29 n+2 n n+2 n+3 n+4 WRITE WITH COUNTER . IH A n+4 Page ...

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... No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. 32. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA during a valid WRITE cycle. Document #: 38-06054 Rev. *A [11, 23, 30, 31, 32 CD2 t CKLZ WRITE READ READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09569V CY7C09579V ...

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... CYC2 t t CH2 CL2 CLK ADDRESS INTERNAL A X ADDRESS R/W ADS CNTEN t t HRST SRST CNTRST DATA IN DATA OUT COUNTER RESET Document #: 38-06054 Rev. *A [23, 25, 30, 31, 32 CD1 WRITE READ ADDRESS 0 ADDRESS 0 CY7C09569V CY7C09579V n READ READ ADDRESS 1 ADDRESS n A n+1 n Page ...

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... CA2 READ WITH t COUNTER DC [33, 34, 36 n+1 t HCN t CA1 n+1 READ WITH t DC COUNTER is extended by 1 cycle. N CY7C09569V CY7C09579V A A n+2 n SAD HAD t t SCN HCN Q n+1 COUNTER READ WITH COUNTER HOLD A A n+3 n SAD HAD t t SCN HCN ...

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... R/W ADS CNTEN CNTRST CY7C09569V CY7C09579V Operation [40] Deselected Write [40] Read Outputs Disabled Mode Operation Reset Counter Reset Load Address Load into Counter Hold + External Address Blocked - Read Counter Address Readout Hold External Address Blocked - Counter Disabled Incre- Counter Increment ment ...

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... DQ DQ 27R–35R 18R–26R [44] I/O Pins used on 1st Cycle I/O 3L–17L I/O 3R–17R I/O 2R–17R I/O 0R–8R CY7C09569V CY7C09579V I/O Pins used I/O 0R–35R I/O 0R–17R I/O 0R–8R Data on 3rd Cycle Data on 4th Cycle - - DQ DQ 18R–26R 27R–35R ...

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... Figure 1. Counter Operation Diagram Bus Match Operation The right port of the CY7C09569V/09579V 16K/32Kx36 dual- port SRAM can be configured in a 36-bit long-word, 18-bit Note: 45. Even though a logic level applied to a “Don’t Care” input will not change the logical operation of the dual-port, inputs that are temporarily a “Don’t Care” (along with unused inputs) must not be allowed to float ...

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... An internal sub-counter automatically increments the right port multiplexer control when Little or Big Endian operation is in effect. When transferring data in byte (9- bit) bus match format, the unused I/O pins (I/O three-stated. CY7C09569V CY7C09579V ) are 9RQ–35R Page ...

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... Ordering Information 16K x36 3.3V Synchronous Dual-Port SRAM Speed (MHz) Ordering Code 100 CY7C09569V-100AC CY7C09569V-100BBC 83 CY7C09569V-83AC CY7C09569V-83BBC 67 CY7C09569V-67AC CY7C09569V-67BBC 32K x36 3.3V Synchronous Dual-Port SRAM Speed (MHz) Ordering Code 100 CY7C09579V-100AC CY7C09579V-100BBC 83 CY7C09579V-83AC CY7C09579V-83AI CY7C09579V-83BBC CY7C09579V-83BBI 67 CY7C09579V-67AC CY7C09579V-67BBC Document #: 38-06054 Rev. *A ...

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... Package Diagrams Document #: 38-06054 Rev. *A 144-Pin Plastic Thin Quad Flat Pack (TQFP) A144 CY7C09569V CY7C09579V 51-85047-A Page ...

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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 172-Ball BGA BB172 CY7C09569V CY7C09579V 51-85114 ...

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... Document Title: CY7C09569V/CY7C09579V 3.3 16K/ 32K x 36 FLEx36™ Synchronous Dual-Port Static RAM Document Number: 38-06054 Issue REV. ECN NO. Date ** 110213 12/16/01 *A 122304 12/27/02 Document #: 38-06054 Rev. *A Orig. of Change Description of Change SZV Change from Spec number: 38-00743 to 38-06054 RBI Power up requirements added to Maximum Ratings Information ...