CY7C09569V-100AC Cypress Semiconductor Corp, CY7C09569V-100AC Datasheet - Page 12

• Manufacturer Part Number: CY7C09569V-100AC
• Description: IC SRAM 576KBIT 100MHZ 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 576K (16K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 67MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1189

Switching Waveforms
Bank Select Pipelined Read
Left Port Write to Flow-Through Right Port Read
Notes:
Document #: 38-06054 Rev. *A
ADDRESS
17. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this data sheet.
18. B0 = B1 = B2 = B3 = BM = SIZE = ADS = CNTEN = V
19. The same waveforms apply for a right port write to flow-through left port read.
20. CE = B0 = B1 = B2 = B3 = ADS = CNTEN=V
21. OE = V
22. If t
ADDRESS
DATA
DATA
ADDRESS
ADDRESS
DATA
ADDRESS
valid until t
DATA
CCS
OUT(B2)
OUT(B1)
CE
CE
CLK
CLK
R/W
CLK
R/W
OUTR
(B1)
(B1)
(B2)
IL
(B2)
INL
maximum specified, then data from right port READ is not valid until the maximum specified for t
for the right port, which is being read from. OE = V
L
R
R
R
CCS
L
L
L
(B1)
= ADDRESS
+ t
t
t
t
t
SA
SC
SA
SC
CD1
(t
t
t
CWDD
t
SW
SA
SD
A
A
0
0
(B2)
t
CH2
does not apply in this case).
MATCH
VALID
.
(continued)
[17, 18]
t
t
t
t
SW
SA
t
t
t
t
MATCH
CYC2
CCS
HA
HC
HA
HC
t
DC
t
CL2
t
t
t
t
HW
HA
t
HW
HA
HD
IL
; CNTRST= V
A
A
1
1
t
CWDD
t
CD2
IL
, CNTRST = V
t
CD1
IH
IH
[18, 19, 20, 21, 22]
t
SC
.
for the left port, which is being written to.
Q
t
0
SC
IH
A
A
.
2
2
t
t
DC
HC
t
HC
t
CD2
MATCH
VALID
NO
Q
MATCH
A
A
1
3
t
NO
3
DC
t
t
CKLZ
CKHZ
t
t
CD2
DC
CWDD
. If t
t
CD1
CCS
Q
A
A
4
>maximum specified, then data is not
2
4
t
t
t
CKHZ
CD2
CKLZ
CY7C09569V
CY7C09579V
Q
3
Page 12 of 30
A
A
VALID
5
t
5
CKLZ
t
t
CKHZ
CD2
Q
4