CY7C09569V-100AC Cypress Semiconductor Corp, CY7C09569V-100AC Datasheet - Page 22

• Manufacturer Part Number: CY7C09569V-100AC
• Description: IC SRAM 576KBIT 100MHZ 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 576K (16K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 67MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1189

Switching Waveforms
Pipelined Read of State of Address Counter
Flow-Through Read of State of Address Counter
Notes:
Document #: 38-06054 Rev. *A
33. CE = OE = V
34. When reading ADDRESS
35. For Pipelined address counter read, signals from address counter operation table from must be valid for 2 consecutive cycles for x36 and x18 mode and for 3
36. For flow-through address counter read, signals from address counter operation table must be valid for consecutive cycles for x36.
ADDRESS
ADDRESS
INTERNAL
ADDRESS
DATA
INTERNAL
ADDRESS
DATA
CNTEN
CNTEN
consecutive cycles for x9 mode.
ADS
CLK
ADS
CLK
OUT
OUT
t
t
SCN
SAD
t
t
SCN
IL
SAD
t
t
SA
; R/W = CNTRST = V
SA
Q
A
A
x-2
Q
t
t
n
n
HAD
HCN
t
t
x
t
t
HA
HA
HAD
HCN
EXTERNAL
ADDRESS
t
t
EXTERNAL
CH2
ADDRESS
CH1
LOAD
t
LOAD
CYC2
t
OUT
CYC1
t
SCN
in x9 Bus Match mode, readout of A
t
t
CL2
t
CL1
SCN
(continued)
Q
IH
Q
x-1
.
t
HCN
READ COUNTER ADDRESS
A
n
READ COUNTER ADDRESS
t
n
DC
t
t
CA1
HCN
A
n
[33, 34, 35]
Q
A
n
n
t
DC
[33, 34, 36]
t
CA2
N
is extended by 1 cycle.
A
n+1
A
Q
n
n+1
READ WITH
COUNTER
READ WITH
COUNTER
t
t
SAD
t
SCN
SAD
t
t
HCN
HAD
t
A
A
HAD
COUNTER
n+2
n+1
COUNTER
HOLD
Q
HOLD
n+2
t
SCN
t
READ WITH COUNTER
HCN
Q
READ WITH COUNTER
n+1
CY7C09569V
CY7C09579V
A
A
n+3
Q
n+2
Page 22 of 30
n+3
Q
n+2