CY7C09569V-100AC Cypress Semiconductor Corp, CY7C09569V-100AC Datasheet - Page 23

• Manufacturer Part Number: CY7C09569V-100AC
• Description: IC SRAM 576KBIT 100MHZ 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 576K (16K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 67MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1189

Read/Write and Enable Operation
Address Counter Control Operation
Document #: 38-06054 Rev. *A
Notes:
Address
37. “X” = “Don’t Care,” “H” = V
38. ADS, CNTEN, CNTRST = “Don’t Care.”
39. OE is an asynchronous input signal.
40. When CE changes state In the pipelined mode, deselection and read happen in the following clock cycle.
41. Counter operation is independent of CE.
A
A
OE
X
X
X
X
X
H
L
n
n
Previous
Address
A
A
A
X
X
n
n
n
CLK
X
CLK
Inputs
IH
, “L” = V
IL
OE
.
CE
X
X
X
X
L
H
L
L
L
[37, 38, 39]
R/W
X
X
H
X
X
[37, 41]
R/W
X
H
X
L
ADS
H
H
X
L
L
CNTEN
I/O
H
H
X
Outputs
L
L
High-Z
High-Z
D
0
D
OUT
–I/O
IN
35
CNTRST
H
H
H
H
L
Deselected
Write
Read
Outputs Disabled
Hold +
Mode
Reset
Incre-
Read
Load
ment
Hold
[40]
Counter Reset
Address Load into Counter
External Address Blocked -
Counter Address Readout
External Address Blocked -
Counter Disabled
Counter Increment
[40]
Operation
CY7C09569V
CY7C09579V
Operation
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