CY7C09569V-100AC Cypress Semiconductor Corp, CY7C09569V-100AC Datasheet - Page 26

• Manufacturer Part Number: CY7C09569V-100AC
• Description: IC SRAM 576KBIT 100MHZ 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 576K (16K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 67MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1189

Word (18-bit) Operation
Word (18-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
pin is set to a logic “0.” In this mode, 18 bits of data are ported
through I/O
determines the right port data I/O sequencing order (Big Endi-
an or Little Endian).
During word (18-bit) bus size operation, a logic LOW applied
to the BE pin will select Little Endian operation. In this case,
the least significant data word is read from the right port first
or written to the right port first. A logic “1” on the BE pin during
word (18-bit) bus size operation will select Big Endian opera-
tion resulting in the most significant data word being trans-
ferred through the right port first. Internally, the data will be
stored in the appropriate 36-bit LSB or MSB I/O memory loca-
tion. Device operation requires a minimum of two clock cycles
to read or write during word (18-bit) bus size operation. An
internal sub-counter automatically increments the right port
multiplexer control when Little or Big Endian operation is in
effect.
Byte (9-bit) Operation
Byte (9-bit) bus sizing operation is enabled when Bus Match
Select (BM) is set to a logic “1” and the Bus Size Select (SIZE)
Document #: 38-06054 Rev. *A
0R–17R
. The level applied to the Big Endian (BE) pin
pin is set to a logic “1.” In this mode, 9 bits of data are ported
through I/O
Big Endian and Little Endian data sequencing is available for
dual-port operation. The level applied to the Big Endian pin
(BE) under these circumstances will determine the right port
data I/O sequencing order (Big or Little Endian). A logic LOW
applied to the BE pin during byte (9-bit) bus size operation will
select Little Endian operation. In this case, the least significant
data byte is read from the right port first or written to the right
port first. A logic “1” on the BE pin during byte (9-bit) bus size
operation will select Big Endian operation resulting in the most
significant data word to be transferred through the right port
first. Internally, the data will be stored in the appropriate 36-bit
LSB or MSB I/O memory location. Device operation requires
a minimum of four clock cycles to read or write during byte (9-
bit) bus size operation. An internal sub-counter automatically
increments the right port multiplexer control when Little or Big
Endian operation is in effect. When transferring data in byte (9-
bit) bus match format, the unused I/O pins (I/O
three-stated.
0R–8R
.
CY7C09569V
CY7C09579V
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9RQ–35R
) are