CY7C09569V-100AC Cypress Semiconductor Corp, CY7C09569V-100AC Datasheet - Page 20

• Manufacturer Part Number: CY7C09569V-100AC
• Description: IC SRAM 576KBIT 100MHZ 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09569V-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 576K (16K x 36)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Density: 576Kb
• Access Time (max): 12.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 67MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 14b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 385mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Word Size: 36b
• Number Of Words: 16K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1189

Switching Waveforms
Counter Reset (Pipelined Outputs)
Notes:
Document #: 38-06054 Rev. *A
30. CE = B0 = B1 = B2 = B3 = V
31. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
32. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals. Ideally, DATA
INTERNAL
ADDRESS
ADDRESS
DATA
CNTRST
DATA
CNTEN
during a valid WRITE cycle.
ADS
R/W
CLK
OUT
[32]
IN
t
SRST
A
x
t
HRST
t
COUNTER
CH2
RESET
t
CYC2
IL
.
t
CL2
(continued)
t
SW
t
SD
D
0
t
t
HW
HD
ADDRESS 0
[11, 23, 30, 31, 32]
WRITE
0
t
CKLZ
ADDRESS 0
READ
ADDRESS 1
t
CD2
READ
1
Q
A
0
n
ADDRESS A
t
READ
CD2
OUT
A
t
should be in the High-Impedance state
SA
n
n
A
Q
m
1
t
ADDRESS A
HA
READ
CY7C09569V
CY7C09579V
A
m
m
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Q
A
n
p
A
p