MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 10

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Ball Descriptions
Table 3:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
54-Ball VFBGA 90-Ball VFBGA
H1, G3, H9, G2,
H7, H8, J8, J7,
J3, J2, H3, H2,
F7, F8, F9
G7, G8
F1, E8
G9
G1
F2
F3
VFBGA Ball Descriptions
G1, G2, G3, H1,
G8, G9, F7, F3,
H2, J3, G7, H9
K9, K1, F8, F2
K7, J9, K8
J7, H8
J1
J2
J8
RAS#, WE#
DQM[33:0]
Symbol
BA[1:0]
A[12:0]
LDQM,
UDQM
CAS#,
CKE
CLK
CS#
Input
Input
Input
Input
Input
Input
Input
Type
Clock: CLK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides precharge power-
down and SELF REFRESH operation (all banks idle), ACTIVE
power-down (row active in any bank), Deep power-down (all
banks idle), or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters
power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input
buffers, including CLK, are disabled during power-down and self
refresh modes, providing low standby power.
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for external
bank selection on systems with multiple banks. CS# is considered
part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input/output mask: DQM is sampled HIGH and is an input mask
signal for write accesses and an output enable signal for read
accesses. Input data is masked during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) during a
READ cycle. For the x16, LDQM corresponds to DQ[7:0] and
UDQM corresponds to DQ[16:8]. For the x32, DQM0 corresponds
to DQ[7:0], DQM1 corresponds to DQ[15:8], DQM2 corresponds
to DQ[23:16], and DQM3 corresponds to DQ[31:24]. DQM[3:0]
(or LDQM and UDQM if x16) are considered same state when
referenced as DQM. DQM loading is designed to match that of
DQ balls.
Bank address input(s): BA[1:0] define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. These
balls also provide the op-code during a LOAD MODE REGISTER
(LMR) command. BA[1:0] become “Don’t Care” when registering
an ALL BANK PRECHARGE (A10 HIGH).
Address inputs: A[12:0] are sampled during the ACTIVE
command (row-address A[12:0] and READ/WRITE command
(column-address A[8:0] (x32); column-address A[8:0] (x16); with
A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be
precharged (A10 HIGH) or bank selected by BA[1:0]. The address
inputs also provide the op-code during a LMR command.
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile SDRAM
Description
©2006 Micron Technology, Inc. All rights reserved.
Ball Descriptions