MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 25

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 12:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
Consecutive READ Bursts
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A continuous page burst will proceed until terminated (at the end of the
page, it will wrap to the start address and continue).
Data from any READ burst may be truncated with a subsequent READ command, and
data from a fixed-length READ burst may be immediately followed by data from a READ
command. In either case, a continuous flow of data can be maintained. The first data
element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst that is being truncated. The new READ com-
mand should be issued x cycles before the clock edge at which the last desired data ele-
ment is valid, where x = CL - 1.
Figure 7 on page 16 shows for CL of two and three; data element n + 3 is either the last of
a burst of four or the last desired of a longer burst. The 256Mb SDRAM uses a pipelined
architecture. A READ command can be initiated on any clock cycle following a previous
READ command. Full-speed random read accesses can be performed to the same bank,
as shown in Figure 12 on page 25, or each subsequent READ may be performed to a dif-
ferent bank.
COMMAND
COMMAND
ADDRESS
ADDRESS
CLK
CLK
DQ
DQ
T0
T0
BANK,
COL n
BANK,
READ
COL n
READ
CL = 2
T1
T1
NOP
NOP
CL = 3
25
T2
T2
NOP
NOP
D
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
NOP
D
D
n + 1
OUT
OUT
n
256Mb: x16, x32 Mobile SDRAM
T4
T4
BANK,
BANK,
READ
COL b
READ
COL b
X = 1 cycle
D
n + 2
D
n + 1
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
D
D
n + 2
n + 3
OUT
OUT
©2006 Micron Technology, Inc. All rights reserved.
T6
T6
NOP
NOP
D
n + 3
D
OUT
OUT
b
DON’T CARE
Operations
T7
NOP
D
OUT
b