MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 27

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 14:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
READ-to-WRITE
Note:
not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during
T4 (as in Figure 15 on page 28) then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.
The DQM signal must be de-asserted prior to the WRITE command (DQM latency is
zero clocks for input buffers) to ensure that the written data is not masked. Figure 12 on
page 25 shows the case where the clock frequency allows for bus contention to be
avoided without adding a NOP cycle, and Figure 13 on page 26 shows the case where the
additional NOP is needed.
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE com-
mand to the same bank (provided that auto precharge was not activated). The PRE-
CHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 16 on page 28 for
each possible CL; data element n + 3 is either the last of a burst of four or the last desired
of a longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE com-
mand issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or continuous
page bursts.
COMMAND
ADDRESS
CL = 3. The READ command may be to any bank, and the WRITE command may be to any
bank. If a burst of one is used, then DQM is not required.
DQM
CLK
DQ
T0
BANK,
COL n
READ
T1
NOP
T2
27
NOP
t
RP is met. Note that part of the row precharge time is
T3
NOP
D
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t HZ
OUT
t CK
n
DON’T CARE
T4
BANK,
COL b
WRITE
256Mb: x16, x32 Mobile SDRAM
D
IN
b
t
DS
©2006 Micron Technology, Inc. All rights reserved.
Operations