MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 52

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
1. All voltages referenced to V
2. This parameter is sampled. V
3.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured for 1.8V at 0.9V with equivalent load:
0.9V; f = 1 MHz.
I
with minimum cycle time and the outputs open.
operation over the full temperature range (–40°C ≤ T
ensured.
commands, before proper device operation is ensured. (V
ered up simultaneously. V
REFRESH command wake-ups should be repeated any time the
ment is exceeded.
sit between V
Test loads with full DQ driver strength. Performance will vary with actual system DQ
bus capacitive loading, termination, and programmed drive strength.
t
a reference to V
High-Z.
point. If the input transition time is longer than
enced at V
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
Q
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
specifications are tested after the device is properly initialized.
is dependent on output loading and cycle rates. Specified values are obtained
DD
current will increase or decrease proportionally according to the amount of
t
CK = 7.5ns for -75,
IL,max
IH
20pF
and V
DD
OH
and V
tests have V
or V
IL
IH,min
IH
(or between V
OL
or V
t
. The last valid data element will meet
52
SS
SS
T = 1ns.
and no longer at the V
t
t
.
t
WR.
CK = 8ns for -8, at CL = 3.
CKS; clock(s) specified as a reference only at minimum
and V
IL
t
DD
WR plus
IL
levels.
, V
and V
DDQ
SSQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
IH
and V
t
must be at same potential.) The two AUTO
= +1.8V; T
RP; clock(s) specified as a reference only at
, with timing referenced to V
256Mb: x16, x32 Mobile SDRAM
IH
) in a monotonic manner.
t
A
IH
T (MAX), then the timing is refer-
= 25°C; ball under test biased at
/2 crossover point.
A
≤ +85°C for T
DD
©2006 Micron Technology, Inc. All rights reserved.
and V
t
REF refresh require-
DDQ
t
OH before going
A
IH
on IT parts) is
/2 = crossover
must be pow-
Notes