MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 12

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Initialization
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
10. Issue a LOAD MODE REGISTER command with BA1=0, and BA0=0, to program the
11. Wait
12. Issue a LOAD MODE REGISTER command with BA1 = 1, and BA0 = 0, to program the
13. Wait
1. Simultaneously apply power to V
2. After power supplies have settled, apply a stable clock signal. Stable clock is defined as
3. Wait at least 100µs. During this period NOP or COMMAND INHIBIT commands
4. Preform a PRECHARGE ALL command to place the SDRAM into an all banks idle
5. Wait at least
6. Issue an AUTO REFRESH command.
7. Wait at least
8. Issue an Auto Refresh command.
9. Wait at least
In general, a 256Mb SDRAM is quad-bank DRAM that operates at 1.8V and includes a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK).
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the
bank, A[12:0] select the row for x16, and A[11:0] select the row for x32). The address bits
(A[8:0] for x16 and A[8:0] for x32) registered coincident with the READ or WRITE com-
mand are used to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections pro-
vide detailed information covering device initialization, register definition, command
descriptions, and device operation.
SDRAM must be powered up and initialized in a predefined manner. Operational proce-
dures other than those specified may result in undefined operation. The initialization for
mobile SDRAM is as follows.
The Mobile SDRAM is now initialized and can accept any valid command.
a signal cycling within timing constraints specified for the clock pin.
should be applied. No other command other than NOP or COMMAND INHIBIT is
allowed during this period.
state.
be applied.
are allowed.
are allowed.
mode register with desired values.
ing this time.
extended mode register with desired values.
ing this time.
t
t
MRD time. Only NOP or COMMAND INHIBIT commands may be applied dur-
MRD time. Only NOP or COMMAND INHIBIT commands may be applied dur-
t
RP time. During this time NOP or COMMAND INHIBIT commands must
t
t
RFC time, during which only NOP or COMMAND INHIBIT commands
RFC time, during which only NOP or COMMAND INHIBIT commands
12
DD
and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DDQ
256Mb: x16, x32 Mobile SDRAM
.
Functional Description
©2006 Micron Technology, Inc. All rights reserved.