MT48H8M32LFB5-75:H Micron Technology Inc, MT48H8M32LFB5-75:H Datasheet - Page 43

• Manufacturer Part Number: MT48H8M32LFB5-75:H
• Description: IC SDRAM 256MBIT 133MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H8M32LFB5-75:H

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 256M (8Mx32)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.95 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 8:
PDF:09005aef8219eeeb/Source: 09005aef8219eedd
256mb_x16_sdram_y36m_1.fm - Rev G 6/09 EN
(auto precharge
(auto precharge
Row activating,
Current State
precharging
precharge)
precharge)
(with auto
(with auto
active, or
disabled)
disabled)
Write
Write
Read
Read
Any
Idle
Truth Table – Current State Bank n, Command to Bank m
Notes: 1–6; notes appear below and on next page
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes: 1. This table applies when CKE
RAS# CAS# WE# Command (Action)
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
2. This table describes alternate bank operation, except where noted; i.e., the current state is
3. Current state definitions:
4. AUTO REFRESH, SELF REFRESH and LMR commands may only be issued when all banks are
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
Idle:
Row active:
Read:
Write:
Read w/auto-
precharge enabled:
Write w/auto-
precharge enabled:
after
for bank n and the commands shown are those allowed to be issued to bank m (assuming
that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
idle.
represented by the current state only.
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
t
XSR has been met (if the previous state was self refresh).
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
The bank has been precharged, and
A row in the bank has been activated, and
data bursts/accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and
has not yet terminated or been terminated.
Starts with registration of a READ command with auto precharge
enabled and ends when
will be in the idle state.
Starts with registration of a WRITE command with auto precharge
enabled and ends when
will be in the idle state.
43
n-1
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mb: x16, x32 Mobile SDRAM
t
t
RP has been met. Once
RP has been met. Once
n
is HIGH (see Table 6 on page 40) and
t
RP has been met.
©2006 Micron Technology, Inc. All rights reserved.
t
RCD has been met. No
t
t
RP is met, the bank
RP is met, the bank
Truth Tables
7, 13, 14
7, 13, 15
7, 13, 16
7, 13, 17
Notes
7, 11
7, 12
7, 8
7, 9
10
10
10
10
7
7