N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 134

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XIP Operations
Note:
10.2
Note:
134/157
DQ0
DQ1
DQ3
DQ2
Vd
S
NVCR check: XIP enabled
Figure 103. XIP mode directly after power on
Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP
mode and return to standard read mode.
Enter XIP mode by setting the Volatile Configuration Register
To use the Volatile Configuration Register method to enter XIP mode, it is necessary to write
a 0 to bit 3 of the Volatile Configuration Register to make the device ready to enter XIP
mode (2). This instruction doesn't permit to enter XIP state directly: a Fast Read instruction
(either Single, Dual or Quad) is needed once to start the XIP Reading.
After the Fast Read instruction (Single, Dual or Quad) the XIP confirmation bit must be set
to 0. (first bit on DQ0 during the first dummy cycle after the address has been received),
Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory
codify the first 3 bytes received on the input pin(s) directly as an address, without any
instruction code, and after the dummy clock cycles (configurable) directly outputs the data.
For example to enable the XIP (without enter) with six dummy clock cycles, the pattern in
Table 29.: VCR XIP bits setting example
for example, in XIP mode from extended SPI read mode by mean of Quad Input Output Fast
Read instruction, as described in
For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not
necessary to set the Volatile Configuration Register bit 3 to enter in XIP mode: it is possible
to enter directly in XIP mode by setting XIP Confirmation bit to 0 during the first dummy
clock cycle after a fast read instruction. See
t
VSI
(<100μ)
C
Mode 3
Mode 0
A23-16 A15-8 A7-0
0
4
5
6
7
1
2
3
0
1
2
6
7
4
5
Table 29.: VCR XIP bits setting
3
2
3
0
1
4
4
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
must be issued, and after that it is possible to enter,
5
0
1
2
3
6
Xb
Section 16: Ordering
Dummy (ex.: 6)
7
8
9 10 11 12 13 14
Byte 1
6
7
4
5
IO switches from Input to Output
Quad_XIP_After_Power-On
1
2
3
0
©2010 Micron Technology, Inc. All rights reserved.
example.
Byte 2
5
6
7
4
information.
15 16
1
2
3
0
6
7
4
5
N25Q128 - 3 V