N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 63

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
9.1.7
Note:
DQ0
DQ0
DQ1
DQ1
C
S
C
S
Mode 3
Mode 0
Figure 15. Dual I/O Fast Read instruction sequence
Quad Output Fast Read
The Quad Output Fast Read (QOFR) instruction is very similar to the Dual Output Fast
Read (DOFR) instruction, except that the data are shifted out on four pins (pin DQ0, pin
DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1) instead of only two. Outputting the data on
four pins instead of one doubles the data transfer bandwidth compared to the Dual Output
Fast Read (DOFR) instruction.
The device is first selected by driving Chip Select (S) Low. The instruction code for the Quad
Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable
number of dummy clock cycles, each bit being latched-in during the rising edge of Serial
Clock (C). Then the memory contents, at that address, are shifted out on pin DQ0, pin DQ1,
pin W/VPP/DQ2 and pin HOLD/DQ3 (1) at a maximum frequency fC, during the falling edge
of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out on pin DQ0, pin DQ1, pin
W/VPP/DQ2 and pin HOLD/DQ3 (1). The whole memory can, therefore, be read with a
single Quad Output Fast Read (QOFR) instruction.
When the highest address is reached, the address counter rolls over to 00 0000h, so that
the read sequence can be continued indefinitely.
Reset functionality is available instead of Hold in devices with a dedicated part number. See
Section 16: Ordering
27 28 29
IO switches from Input to Output
6
7
Byte 1
4
5
0
30
2
3
1
31 32 33 34 35 36 37 38 39 40 41
0
1
2
Instruction
6
7
3
Byte 2
4
5
information.
4
2
3
5
0
1
6
6
7
7
4
5
22 20 18 16
23 21 19 17 15 13 11 9
Byte 3
8
2
3
9 10 11 12 13 14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
0
1
6
7
24-bit Address
4
Byte 4
5
14 12 10 8
42
2
3
43
0
1
6
7
15 16 17 18 19 20
6
7
©2010 Micron Technology, Inc. All rights reserved.
4
5
2
3
0
1
Dummy Cycles
Instructions
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