N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 76

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instructions
9.1.20
76/157
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. Alternately, it
is possible to read the Flag Status Register to check if the internal modify cycle is finished.
A Sector Erase (SE) instruction issued to a sector that is hardware or software protected is
not executed
A Sector Erase cycle can be paused by mean of Program/Erase Suspend (PES) instruction
and resumed by mean of Program/Erase Resume (PER) instruction.
Figure 29. Sector Erase instruction sequence
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the
entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset. Alternately, it is possible to read the
Flag Status Register to check if the internal modify cycle is finished.
The Bulk Erase (BE) instruction is ignored if one or more sectors are hardware or software
protected. The Bulk Erase cycle cannot be paused by a Program/Erase Suspend (PES)
instruction.
Figure 30. Bulk Erase instruction sequence
S
C
DQ0
S
C
DQ0
0
1
2
Instruction
0
3
1
4
2
5
Instruction
6
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7
4
MSB
23 22
8
5
9
6
24 Bit Address
7
2
29 30 31
1
0
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N25Q128 - 3 V