N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 135

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
Note:
10.3
DQ0
DQ3
DQ1
DQ2
C
S
Mode 3
Mode 0
Table 29.
Figure 104. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example)
Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP
mode and return to standard read mode.
XIP mode hold and exit
The XIP mode does require at least one additional clock cycle to allow the XIP Confirmation
bit to be sent to the memory on DQ0 during the first dummy clock cycle.
The device decodes the XIP Confirmation bit with the scheme:
In Dual I/O XIP mode, the values of DQ1 during the first dummy clock cycle after the
addresses is always Don't Care.
In Quad I/O XIP mode, the values of DQ3, DQ2 and DQ1 during the first dummy clock cycle
after the addresses are always Don't Care.
XIP Confirmation bit=0 means to hold XIP Mode
XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, that
means codifying the first byte after the next chip select as an instruction code.
0
‘1’
Don’t Care
Don’t Care
1
81h (WRVCR opcode)
2
Instruction
VCR XIP bits setting example
3
4
5
6
7
A23-16 A15-8 A7-0
4
5
6
7
8
0
1
2
3
9 10 11 12 13 14
6
7
4
5
0
1
2
3
4
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
6 dummy
+ 0110
cycles
2
3
0
1
Xb
Dummy (ex.: 6)
15 16
Ready for
17 18
XIP
0
19
20
6
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7
4
5
Byte 1
IO switches from Input to Output
21
1
2
3
0
22
6
7
4
5
XIP_VCR
Byte 2
Reserved
23
1
2
3
0
000
XIP Operations
5
6
7
4
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