N25Q128A13BF840F NUMONYX, N25Q128A13BF840F Datasheet - Page 75

• Manufacturer Part Number: N25Q128A13BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of N25Q128A13BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

N25Q128 - 3 V
9.1.18
9.1.19
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code, and three address bytes on Serial Data input (DQ0). Any address
inside the subsector is a valid address for the Subsector Erase (SSE) instruction. Chip
Select (S) must be driven Low for the entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as
Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is
tSSE) is initiated. While the Subsector Erase cycle is in progress, the Status Register may
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
Alternately, it is possible to read the Flag Status Register to check if the internal modify cycle
is finished.
A Subsector Erase (SSE) instruction issued to a sector that is hardware or software
protected, is not executed. Any Subsector Erase (SSE) instruction, while an Erase or
Program cycle is in progress, is rejected without having any effects on the cycle that is in
progress. A Subsector Erase cycle can be paused by a Program/Erase Suspend (PES)
instruction and resumed by a Program/Erase Resume (PER) instruction.
Figure 28. Subsector Erase instruction sequence
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (DQ0). Any address inside
the sector is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be
driven Low for the entire duration of the sequence.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
S
C
DQ0
0
1
2
Instruction
3
4
5
6
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MSB
23 22
8
9
24 Bit Address
2
29 30 31
1
0
©2010 Micron Technology, Inc. All rights reserved.
Instructions
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