PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 12

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
Table 5.
[1]
[2]
UJA1076_2
Product data sheet
Bit
15:13
12
11:10
9
8
7
6
5
4
3:0
Bit LHWC is set to 1 after a reset.
Bit LHC is set to 1 after a reset, if LHWC was set to 1 prior to the reset.
Symbol
A2, A1, A0 R
RO
MC
LHWC
LHC
ENC
reserved
WBC
PDC
reserved
Mode_Control register
[2]
[1]
6.2.4 Mode_Control register
Access Power-on
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
default
001
0
00
1
0
0
0
0
0
0000
All information provided in this document is subject to legal disclaimers.
Description
register address
access status
mode control
limp home warning control
limp home control
enable control
wake bias control
power distribution control
0: register set to read/write
1: register set to read only
00: Standby mode
01: Sleep mode
10: Normal mode; V2 off
11: Normal mode; V2 on
0: no limp home warning
1: limp home warning is set; next reset will activate LIMP output
0: LIMP pin set floating
1: LIMP pin driven LOW
0: EN pin driven LOW
1: EN pin driven HIGH in Normal mode
0: WBIAS floating if WSEn = 0; 16 ms sampling if WSEn = 1
1: WBIAS on if WSEn = 0; 64 ms sampling if WSEn = 1
0: V1 threshold current for activating the external PNP transistor; load current
rising; I
PNP transistor; load current falling; I
1: V1 threshold current for activating the external PNP transistor; load current
rising; I
PNP transistor; load current falling; I
Rev. 02 — 27 May 2010
th(act)PNP
th(act)PNP
= 85 mA; V1 threshold current for deactivating the external
= 50 mA; V1 threshold current for deactivating the external
High-speed CAN core system basis chip
th(deact)PNP
th(deact)PNP
= 50 mA; see
= 15 mA; see
UJA1076
© NXP B.V. 2010. All rights reserved.
Figure 7
Figure 7
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