PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 14

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
Table 6.
Table 7.
[1]
UJA1076_2
Product data sheet
Bit
0
Bit
15:13
12
11
10
9:8
7
6
5
4
3
2:0
An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.
Symbol
WSE2
Symbol
A2, A1, A0 R
RO
V1UI
V2UI
reserved
CI
WI1
POSI
WI2
CWI
reserved
Int_Control register
Int_Status register
6.2.6 Int_Status register
Access Power-on
R/W
Access Power-on
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
[1]
default
0
default
011
0
0
0
00
0
0
1
0
0
000
All information provided in this document is subject to legal disclaimers.
Description
WAKE2 sample enable
Description
register address
access status
V1 undervoltage interrupts
V2 undervoltage interrupts
cyclic interrupt
wake-up interrupt 1
power-on status interrupt
wake-up interrupt 2
CAN wake-up interrupt
0: sampling continuously
1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled
by WBC)
0: register set to read/write
1: register set to read only
0: no V1 undervoltage warning interrupt pending
1: V1 undervoltage warning interrupt pending
0: no V2 undervoltage warning interrupt pending
1: V2 undervoltage warning interrupt pending
0: no cyclic interrupt pending
1: cyclic interrupt pending
0: no wake-up interrupt 1 pending
1: wake-up interrupt 1 pending
0: no power-on interrupt pending
1: power-on interrupt pending
0: no wake-up interrupt 2 pending
1: wake-up interrupt 2 pending
0: no CAN wake-up interrupt pending
1: CAN wake-up interrupt pending
Rev. 02 — 27 May 2010
High-speed CAN core system basis chip
UJA1076
© NXP B.V. 2010. All rights reserved.
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