PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 22

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
UJA1076_2
Product data sheet
6.7.3.1 TXDC dominant time-out function
6.7.3.2 Pull-up on TXDC pin
6.7.2 Split circuit
6.7.3 Fail-safe features
6.8 Local wake-up input
Pin SPLIT provides a DC stabilized voltage of 0.5V
only. Pin SPLIT is floating in CAN Lowpower and Off modes. The V
used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the
center tap of the split termination (see
A transceiver in the network that is not supplied and that generates a significant leakage
current from the bus lines to ground, can result in a recessive bus voltage of < 0.5V
this event, the split circuit will stabilize the recessive voltage at 0.5V
transmission will not generate a step in the common-mode signal which would lead to
poor ElectroMagnetic Emission (EME) performance.
A TXDC dominant time-out timer is started when pin TXDC is forced LOW. If the LOW
state on pin TXDC persists for longer than the TXDC dominant time-out time (t
the transmitter will be disabled, releasing the bus lines to recessive state. This function
prevents a hardware and/or software application failure from driving the bus lines to a
permanent dominant state (blocking all network communications). The TXDC dominant
time-out timer is reset when pin TXDC goes HIGH. The TXDC dominant time-out time
also defines the minimum possible bit rate of 10 kbit/s.
Pin TXDC has an internal pull-up towards V
pin is left floating.
The SBC provides 2 local wake-up pins (WAKE1 and WAKE2). The edge sensitivity
(falling, rising or both) of the wake-up pins can be configured independently via the WIC1
and WIC2 bits in the Int_Control register
wake-up via the wake-up pins. When wake-up is enabled, a valid wake-up event on either
of these pins will cause a wake-up interrupt to be generated in Standby mode or Normal
Fig 10. Stabilization circuitry and application using the SPLIT pin
All information provided in this document is subject to legal disclaimers.
V
in normal mode;
otherwise floating
SPLIT
Rev. 02 — 27 May 2010
= 0.5 V
CC
Figure
R
R
V2
GND
Table
UJA1076
V1
10).
High-speed CAN core system basis chip
to ensure a safe defined state in case the
6). These bits can also be used to disable
SPLIT
CANL
V2
CANH
. It is activated in CAN Active mode
60 Ω
60 Ω
015aaa121
SPLIT
V2
. So a start of
UJA1076
© NXP B.V. 2010. All rights reserved.
circuit can be
to(dom)TXDC
22 of 47
V2
. In
),