PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 36

• Manufacturer Part Number: PCF8534AHL/1,518
• Description: IC LCD DISPLAY DRVR 60SEG 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AHL/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-5058-2; 935289852518

NXP Semiconductors
Table 11.
T
with respect to ground; positive currents flow in the IC; typical values are given at V
UJA1076_2
Product data sheet
Symbol
t
t
t
t
t
t
t
t
t
Wake bias output; pin WBIAS
t
t
Watchdog
t
t
d(TXDCL-RXDCL)
d(TXDC-busdom)
d(TXDC-busrec)
d(busdom-RXDC)
d(busrec-RXDC)
wake(busdom)min
wake(busrec)min
to(wake)
to(dom)TXDC
WBIASL
cy
trig(wd)1
trig(wd)2
vj
=
−
40 °C to +150
Dynamic characteristics
Parameter
delay time from TXDC LOW
to RXDC LOW
delay time from TXDC to bus
dominant
delay time from TXDC to bus
recessive
delay time from bus dominant
to RXDC
delay time from bus recessive
to RXDC
minimum bus dominant
wake-up time
minimum bus recessive
wake-up time
wake-up time-out time
TXDC dominant time-out time CAN online; V
WBIAS LOW time
cycle time
watchdog trigger time 1
watchdog trigger time 2
°
C; V
BAT
= 4.5 V to 28 V; V
…continued
All information provided in this document is subject to legal disclaimers.
BAT
Conditions
50 % V
V
R
C
C
V
R
C
V
R
C
V
R
C
C
V
R
C
C
first pulse (after first recessive) for
wake-up on pins CANH and CANL
Sleep mode
second pulse for wake-up on pins
CANH and CANL
first pulse for wake-up on pins CANH
and CANL; Sleep mode
second pulse (after first dominant) for
wake-up on pins CANH and CANL
between wake-up and confirm
messages; Sleep mode
V
WBC = 1
WBC = 0
Normal mode
watchdog Window mode only
Normal, Standby and Sleep modes
watchdog Window mode only
V2
V2
V2
V2
V2
TXDC
(CANH-CANL)
(CANH-CANL)
RXDC
(CANH-CANL)
(CANH-CANL)
(CANH-CANL)
(CANH-CANL)
(CANH-CANL)
(CANH-CANL)
RXDC
(CANH-CANL)
(CANH-CANL)
RXDC
> V
Rev. 02 — 27 May 2010
= 4.5 V to 5.5 V
= 4.5 V to 5. 5 V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
V1
= 0 V
=15 pF; f
= 15 pF
= 15 pF
TXDC
; V
BAT
to 50 % V
= 60 Ω
= 100 pF
= 60 Ω
= 100 pF
= 60 Ω
= 100 pF
= 60 Ω
= 100 pF
= 60 Ω
= 100 pF
> V
V2
TXDC
= 4.5 V to 5.5 V
V2
; R
= 250 kHz
(CANH-CANL)
RXDC
High-speed CAN core system basis chip
BAT
= 45
= 14 V; unless otherwise specified.
Ω
[1]
[3]
to 65
Min
60
-
-
-
-
0.5
0.5
0.5
0.5
0.4
1.8
227
58.1
14.5
0.45 ×
NWP
0.9 ×
NWP
Ω
; all voltages are defined
[2]
[2]
Typ
-
70
90
75
95
-
-
-
-
-
-
-
-
-
-
-
UJA1076
© NXP B.V. 2010. All rights reserved.
Max
235
-
-
-
-
3
3
3
3
1.2
4.5
278
71.2
17.8
0.555 ×
NWP
1.11 ×
NWP
[2]
[2]
36 of 47
Unit
ns
ns
ns
ns
ns
μs
μs
μs
μs
ms
ms
μs
ms
ms
ms
ms