PCF8534AHL/1,518 NXP Semiconductors, PCF8534AHL/1,518 Datasheet - Page 5

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PCF8534AHL/1,518

Manufacturer Part Number
PCF8534AHL/1,518
Description
IC LCD DISPLAY DRVR 60SEG 80LQFP
Manufacturer
NXP Semiconductors
Datasheets

Specifications of PCF8534AHL/1,518

Package / Case
80-LQFP
Display Type
LCD
Configuration
60 Segment
Interface
I²C
Current - Supply
8µA
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Digits
30
Number Of Segments
240
Maximum Clock Frequency
400 KHz
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Power Dissipation
400 mW
Maximum Operating Temperature
+ 85 C
Maximum Supply Current
50 mA
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Digits Or Characters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-5058-2
935289852518

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCF8534AHL/1,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
5. Pinning information
UJA1076_2
Product data sheet
5.1 Pinning
5.2 Pin description
Table 2.
Symbol
i.c.
i.c.
i.c.
V1
i.c.
RSTN
INTN
EN
SDI
SDO
SCK
SCSN
TXDC
RXDC
TEST1
WDOFF
LIMP
Fig 2.
Pin configuration
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
All information provided in this document is subject to legal disclaimers.
WDOFF
Description
internally connected; should be left floating
internally connected; should be left floating
internally connected; should be left floating
voltage regulator output for the microcontroller (5 V or 3.3 V depending on
SBC version)
internally connected; should be left floating
reset input/output to and from the microcontroller
interrupt output to the microcontroller
enable output
SPI data input
SPI data output
SPI clock input
SPI chip select input
CAN transmit data input
CAN receive data output
test pin; pin should be connected to ground
WDOFF pin for deactivating the watchdog
limp home output
TEST1
RXDC
SCSN
RSTN
TXDC
Rev. 02 — 27 May 2010
INTN
SDO
SCK
SDI
EN
i.c.
i.c.
i.c.
V1
i.c.
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
UJA1076
High-speed CAN core system basis chip
015aaa109
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BAT
VEXCTRL
TEST2
VEXCC
WBIAS
i.c.
i.c.
i.c.
SPLIT
GND
CANL
CANH
V2
WAKE2
WAKE1
LIMP
UJA1076
© NXP B.V. 2010. All rights reserved.
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