PCF8534AH/1,518 NXP Semiconductors, PCF8534AH/1,518 Datasheet - Page 31

• Manufacturer Part Number: PCF8534AH/1,518
• Description: IC LCD DVR UNVRSL LOW-MUX 80LQFP
• Manufacturer: NXP Semiconductors

Specifications of PCF8534AH/1,518

• Package / Case: 80-LQFP
• Display Type: LCD
• Configuration: 60 Segment
• Interface: I²C
• Current - Supply: 8µA
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Digits: 30
• Number Of Segments: 240
• Maximum Clock Frequency: 400 KHz
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Power Dissipation: 400 mW
• Maximum Operating Temperature: + 85 C
• Maximum Supply Current: 50 mA
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Digits Or Characters: -
• Lead Free Status / Rohs Status: Details
• Other names: 935284829518; PCF8534AH/1-T; PCF8534AH/1-T

NXP Semiconductors
PCF8534A_3
Product data sheet
Fig 21. Cascaded PCF8534A configuration
V
V
V
CONTROLLER
SS
DD
PROCESSOR/
LCD
MICRO-
MICRO-
HOST
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8534As. Synchronization is guaranteed after a power-on reset. The only time that
SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments or by defining a multiplex mode when PCF8534As with
different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCF8534A asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF8534A to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF8534A are shown in
R
2C
t
r
b
Rev. 03 — 10 November 2008
SYNC
OSC
SYNC
SDA
CLK
SCL
SDA
SCL
CLK
OSC
A0
A0
PCF8534A
A1
PCF8534A
A1
V
V
DD
DD
A2
A2 SA0
SA0
V
V
Universal LCD driver for low multiplex rates
LCD
LCD
V
SS
V
60 segment drives
SS
60 segment drives
4 backplanes
BP0 to BP3
BP0 to BP3
(open-circuit)
Figure
LCD PANEL
22.
PCF8534A
001aah619
© NXP B.V. 2008. All rights reserved.
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