IDT72V51333L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51333L7-5BB8 Datasheet - Page 23

• Manufacturer Part Number: IDT72V51333L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51333L7-5BB8

• Configuration: Dual
• Density: 512Kb
• Access Time (max): 4ns
• Word Size: 18b
• Organization: 4Kx18x8
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 100mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51333L7-5BB8

PAFn FLAG BUS OPERATION
can be configured for up to 8 queues, each queue having its own almost full
status. An active queue has its flag status output to the discrete flags, FF and PAF,
on the write port. Queues that are not selected for a write operation can have
their PAF status monitored via the PAFn bus. The PAFn flag bus is 8 bits wide,
so that all 4 queues can have their status output to the bus. When a single
multi-queue device is used anywhere from 1 to 4 queues may be set-up within
the part, each queue having its own dedicated PAF flag output on the PAFn bus.
Queues 1 through 8 have their PAF status to PAF[0] through PAF[7]
respectively. If less than 8 queues are used then only the associated PAFn
outputs will be required, unused PAFn outputs will be don’t care outputs. When
devices are connected in expansion mode the PAFn flag bus can also be
expanded beyond 8 bits to produce a wider PAFn bus that encompasses all
queues.
to form a single 8 bit bus, i.e. PAF[0] of device 1 will connect to PAF[0] of device
2 etc. When connecting devices in this manner the PAFn can only be driven
by a single device at any time, (the PAFn outputs of all other devices must be
in high impedance state). There are two methods by which the user can select
which device has control of the bus, these are “Direct” (Addressed) mode or
“Polled” (Looped) mode, determined by the state of the FM (flag Mode) input
during a Master Reset.
PAFn BUS EXPANSION - DIRECT MODE
(addressed) mode. In direct mode the user can address the device they require
to control the PAFn bus. The address present on the 3 most significant bits of
the WRADD[5:0] address bus with FSTR (PAF flag strobe), HIGH will be
selected as the device on a rising edge of WCLK. So to address the first device
in a bank of devices the WRADD[5:0] address should be “000xxx” the second
device “001xxx” and so on. The 3 most significant bits of the WRADD[5:0]
address bus correspond to the device ID inputs ID[2:0]. The PAFn bus will
change status to show the new device selected 1 WCLK cycle after device
selection. Note, that if a read or write operation is occurring to a specific queue,
say queue ‘x’ on the same cycle as a PAFn bus switch to the device containing
queue ‘x’, then there may be an extra WCLK cycle delay before that queues
status is correctly shown on the respective output of the PAFn bus. However,
the “active” PAF flag will show correct status at all times.
controlling the PAFn bus can change every WCLK cycle. Also, data present
on the input bus, Din, can be written into a queue on the same WLCK rising edge
that a device is being selected on the PAFn bus, the only restriction being that
a write queue selection and PAFn bus selection cannot be made on the same
cycle.
PAFn BUS EXPANSION– POLLED MODE
mode. In polled mode the PAFn bus automatically cycles through the devices
connected in expansion. In expansion mode one device will be set as the
Master, MAST input tied HIGH, all other devices will have MAST tied LOW. The
master device is the first device to take control of the PAFn bus and place the
PAF status of its queues onto the bus on the first rising edge of WCLK after the
MRS input goes HIGH once a Master Reset is complete. The FSYNC (PAF sync
pulse) output of the first device (master device), will be HIGH for one cycle of
WCLK indicating that it is has control of the PAFn bus for that cycle.
device assuming control of the PAFn bus on the next WCLK cycle. This token
IDT72V51333/72V51343/72V51353 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
The IDT72V51333/72V51343/72V51353 multi-queue flow-control devices
Alternatively, the 8 bit PAFn flag bus of each device can be connected together
If FM is LOW at Master Reset then the PAFn bus operates in Direct
Devices can be selected on consecutive WCLK cycles, that is the device
If FM is HIGH at Master Reset then the PAFn bus operates in Polled (Looped)
The device also passes a “token” onto the next device in the chain, the next
23
passing is done via the FXO outputs and FXI inputs of the devices (“PAFn
Expansion Out” and “PAFn Expansion In”). The FXO output of the first device
connecting to the FXI input of the second device in the chain, the FXO of the
second device connects to the FXI of the third device and so on. The FXO of
the final device in a chain connects to the FXI of the first device, so that once the
PAFn bus has cycled through all devices control is again passed to the first
device. The FXO output of a device will be HIGH for the WCLK cycle it has control
of the bus.
PAEn FLAG BUS OPERATION
can be configured for up to 8 queues, each queue having its own almost empty
status. An active queue has its flag status output to the discrete flags, OV and PAE,
on the read port. Queues that are not selected for a read operation can have
their PAE status monitored via the PAEn bus. The PAEn flag bus is 8 bits wide,
so that all 8 queues can have their status output to the bus.
be set-up within the part, each queue having its own dedicated PAEn flag output
on the PAEn bus. Queues 1 through 8 have their PAE status to PAE[0] through
PAE[7] respectively. If less than 8 queues are used then only the associated
PAEn outputs will be required, unused PAEn outputs will be don’t care outputs.
When devices are connected in expansion mode the PAEn flag bus can also
be expanded beyond 8 bits to produce a wider PAEn bus that encompasses
all queues.
to form a single 8 bit bus, i.e. PAE[0] of device 1 will connect to PAE[0] of device
2 etc. When connecting devices in this manner the PAEn bus can only be driven
by a single device at any time, (the PAEn outputs of all other devices must be
in high impedance state). There are two methods by which the user can select
which device has control of the bus, these are “Direct” (Addressed) mode or
“Polled” (Looped) mode, determined by the state of the FM (flag Mode) input
during a Master Reset.
PAEn BUS EXPANSION- DIRECT MODE
(addressed) mode. In direct mode the user can address the device they require
to control the PAEn bus. The address present on the 3 most significant bits of
the RDADD[6:0] address bus with ESTR (PAE flag strobe), HIGH will be
selected as the device on a rising edge of RCLK. So to address the first device
in a bank of devices the RDADD[6:0] address should be “000xxx” the second
device “001xxx” and so on. The 3 most significant bits of the RDADD[6:0]
address bus correspond to the device ID inputs ID[2:0]. The PAEn bus will
change status to show the new device selected 1 RCLK cycle after device
selection. Note, that if a read or write operation is occurring to a specific queue,
say queue ‘x’ on the same cycle as a PAEn bus switch to the device containing
queue ‘x’, then there may be an extra RCLK cycle delay before that queues
status is correctly shown on the respective output of the PAEn bus. However,
the “active” PAE flag will show correct status at all times.
controlling the PAEn bus can change every RCLK cycle. Also, data can be read
out of a FIFO queue on the same RCLK rising edge that a device is being selected
on the PAEn bus, the only restriction being that a read queue selection and PAEn
bus selection cannot be made on the same cycle.
PAEn BUS EXPANSION- POLLED MODE
(Looped) mode. In polled mode the PAEn bus automatically cycles through the
Please refer to Figure 24, PAFn Bus – Polled Mode for timing information.
The IDT72V51333/72V51343/72V51353 multi-queue flow-control devices
When a single multi-queue device is used anywhere from 1 to 8 queues may
Alternatively, the 8 bit PAEn flag bus of each device can be connected together
If FM is LOW at Master Reset then the PAEn bus operates in Direct
Devices can be selected on consecutive RCLK cycles, that is the device
If FM is HIGH at Master Reset then the PAEn bus operates in Polled
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES